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參數(shù)資料
| 型號(hào)： | LH28F020SU-L |
| 廠商： | Sharp Corporation |
| 英文描述： | 2M (256K 】 8) Flash Memory |
| 中文描述： | 200萬（256K】8）閃存 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大小： | 245K |
| 代理商： | LH28F020SU-L |
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LH28F020SU-L
2M (256K × 8) Flash Memory
4
The LH28F020SU-L15 will be available in a 32-pin,
1.2 mm thick, 8 mm × 20 mm TSOP (Type I) package.
This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed typically within
20 μs. A Block Erase operation erases one of the 16
blocks in typically 0.8 seconds, independent of the other
blocks.
LH28F020SU-L allows to erase all unlocked blocks.
It is desirable in case you have to implement Erase op-
eration maximum 16 times.
LH28F020SU-L enables two-byte serial Write which
is operated by three times command input. This feature
can improve system write performance by up to typi-
cally 17 μs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) provide information on the progress of the
requested operation.
Same as the LH28F008SA, LH28F020SU-L requires
an operation to complete before the next operation can
be requested, also it allows to suspend block erase to
read data from any other block, and allow to resume
erase operation.
The LH28F020SU-L provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or Ap-
plication Code. Each block has an associated non-vola-
tile lock-bit which determines the lock status of the block.
In addition, the LH28F020SU-L has a software controlled
master Write Protect circuit which prevents any modifi-
cations to memory blocks whose lock-bits are set.
When the device power-up, Write Protect Set/
Confirm command must be written. Otherwise, all lock
bits in the device remain being locked, can’t perform
the Write to each block and single Block Erase. Write
Protect Set/Confirm command must be written to re-
flect the actual lock status. However, when the device
power-on, Erase All Unlocked Blocks can be used. If
used, Erase is performed with reflecting actual lock sta-
tus, and after that Write and Block Erase can be used.
The LH28F020SU-L contains Status register to
accomplish various functions:
A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capabil-
ity to the LH28F020SU-L from a LH28F00SA-
based design.
The LH28F020SU-L is specified for a maximum
access time of 150 ns (t
ACC
) at 3.3 V operation (3.0 to
3.6 V) over the commercial temperature range (0 to
+70°C). A corresponding maximum access time of
180 ns (t
ACC
) at 2.7 V (0 to +70°C) is achieved for
reduced power consumption applications.
The LH28F020SU-L incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical I
CC
current is 4 mA at 3.3 V.
A chip reset mode of operation is enabled when whole
CE
, WE
and OE
hold low more than 5 μs. In this mode,
all operations are aborted, WSM is reset and CSR reg-
ister is cleared. When the device power up, this chip
reset operation must be executed to initialize the con-
trol circuit, put the device in chip reset mode to protect
data against noise. Especially, to assume data protec-
tion against switching noise at power up, above chip
reset sequence must be executed. If CE
and or WE
and or OE
and or goes high, chip reset mode will be
finished. It needs more than 620 ns from one of the CE
,
WE
or OE
goes high until output data are valid.
A CMOS Standby mode of operation is enabled when
CE
transitions high with all input control pins at CMOS
levels. In this mode, the device draws an I
CC
standby
current of 80 μA.
Please do not execute reprogramming 0 for the bit
which has already been programmed 0. Overwrite op-
eration may generate unerasable bit. In case of repro-
gramming 0 to the data which has been programmed 1.
program 0 for the bit in which you want to change
data from 1 to 0.
program 1 for the bit which has already been pro-
grammed 0.
For example, changing data from 10111101 to
10111100 requires 11111110 programming.
相關(guān)PDF資料 |
PDF描述 |
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| LH28F020SU-N | 2M (256K 】 8) Flash Memory |
| LH28F040SUTD-Z4 | 4M (512K 】 8) Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F020SU-N | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:2M (256K 】 8) Flash Memory |
| LH28F020SUN-L12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Flash EEPROM |
| LH28F032SUTD-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8/x16 Flash EEPROM Module |
| LH28F040SUTD-Z4 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:4M (512K 】 8) Flash Memory |
| LH28F0I6SCT-L95 | 制造商:Sharp Microelectronics Corporation 功能描述: |
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