參數(shù)資料
型號: LFX125EB-04F256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 33/119頁
文件大?。?/td> 0K
描述: IC FPGA 139K GATES 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 1936
RAM 位總計: 94208
輸入/輸出數(shù): 160
門數(shù): 139000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 105°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
其它名稱: 220-1238
Lattice Semiconductor
ispXPGA Family Data Sheet
16
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-
lar I/O interfaces requires an additional VREF signal. At the system level a termination voltage, VTT, is also required.
Typically an output will be terminated to VTT at the receiving end of the transmission line it is driving.
The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential
standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the
two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices.
For more information on sysIO capability, refer to TN1000, sysIO Usage Guidelines for Lattice Devices.
Figure 19. sysIO Banks per Device
Table 4. Number of I/Os per Bank
Device
Max. Number of I/Os per Bank (N)
XPGA 1200
62
XPGA 500
42
XPGA 200
26
XPGA 125
22
GND
VCCO0
VREF0
GND
VCCO1
VREF1
GND
VCCO5
VREF5
GND
VCCO4
VREF4
GND
V
CCO3
V
REF3
GND
V
CCO2
V
REF2
GND
V
CCO6
V
REF6
GND
I/O
0
I/O
N
I/O 0
I/O N
I/O 0
I/O
0
I/O
N
I/O
N
I/O
0
I/O
N
I/O
0
V
CCO7
V
REF7
Bank 3
Bank 2
Bank 6
Bank 7
Bank
0
Bank
1
Bank
5
Bank
4
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