參數(shù)資料
型號: LFX125EB-04F256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 29/119頁
文件大?。?/td> 0K
描述: IC FPGA 139K GATES 256-BGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPGA®
邏輯元件/單元數(shù): 1936
RAM 位總計: 94208
輸入/輸出數(shù): 160
門數(shù): 139000
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 105°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
其它名稱: 220-1238
Lattice Semiconductor
ispXPGA Family Data Sheet
13
Figure 13. EBR Synchronous Read Timing Diagram
Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high, the
write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock
edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the
synchronous write timing.
Figure 14. EBR Synchronous Write Timing Diagram
Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the
read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15
illustrates the asynchronous read timing. For more information about the EBR, refer to TN1028 ispXPGA Memory
Figure 15. EBR Asynchronous Read Timing Diagram
WE
CLK
CE
DATA
ADDR
OE
Valid Data
Invalid Data
Valid Data
t
EBWEEN
t
EBADDS
t
EBCO
t
EBWES
t
EBCES
t
EBCPW
t
EBOEDIS
t
EBOEEN
t
EBCEH
t
EBWEH
t
EBWEDIS
t
EBADDH
WE
CLK
WRITE
DATA
ADDR
WRITE
t
EBWEH
t
EBADDS
t
EBADDH
t
EBDATAS
t
EBDATAH
t
EBPW
t
EBWES
WE
DATA
ADDR
OE
DATA1
Invalid Data
DATA1
ADDR0
ADDR1
ADDR2
DATA0
t
EBWEEN
t
EBARADO
t
EBOEDIS
t
EBOEEN
t
EBWEDIS
t
EBARAD_H
SELECT
DEVICES
DISCONTINUED
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