LC87F74C8A
No.7825-9/21
Continued from preceding page.
Pin name
I/O
Function
Option
S24/PD0 to S31/PD7
I/O
Segment output for LCD
Can be used as general purpose input/output port (PD)
No
S32/PE0 to S39/PE7
I/O
Segment output for LCD
Can be used as general purpose input/output port (PE)
No
S40/PF0 to S47/PF7
I/O
Segment output for LCD
Can be used as general purpose input/output port (PF)
No
COM0/PL0 to
COM3/PL3
V1/PL4 to V3/PL6
I/O
Common output for LCD
Can be used as general purpose input port (PL)
No
I/O
LCD output bias power supply
Can be used as general purpose input port (PL)
Other functions :
AD input ports : AN12 to AN14
No
RES
I
Reset terminal
No
XT1
I
Input for 32.768kHz crystal oscillation
Other functions :
General purpose input port
AD input port : AN10
When not in use, connect to VDD1
Output for 32.768kHz crystal oscillation
Other functions :
General purpose input port
AD input port : AN11
When not in use, set to oscillation mode and leave open
No
XT2
I/O
No
CF1
I
Input terminal for ceramic oscillator
No
CF2
O
Output terminal for ceramic oscillator
No
Port output Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Option
applies to :
Terminal
Option
Output format
Pull-up resistor
1
CMOS
Programmable (Note 1)
P00 to P07
each bit
2
Nch-open drain
None
1
CMOS
Programmable
P10 to P17
each bit
2
Nch-open drain
Programmable
1
CMOS
Programmable
P30 to P35
each bit
2
Nch-open drain
None
P70
–
None
Nch-open drain
Programmable
P71 to P73
–
None
CMOS
Programmable
P80 to P87
–
None
Nch-open drain
None
S0/PA0 to S47/PF7
–
None
CMOS
Programmable
COM0/PL0 to
COM3/PL3
–
None
Input only
None
V1/PL4 to V3/PL6
–
None
Input only
None
XT1
–
None
Input only
None
XT2
Note 1 : Attachment of Port 0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
* Note 1 : Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
* Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports.
When the VDD2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level.
Therefore, when the VDD2 is not backed up and the port latch is "H" level, the port level is unstable in the
HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the
input buffer.
If VDD2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the
HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
–
None
Output for 32.768kHz crystal oscillation
None