
LC87F74C8A
No.7825-12/21
Electrical Characteristics
/ Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Limits
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
IIH(1)
Port 0, 1, 3, 7, 8
Port A, B, C, D, E, F, L
Output disabled
Pull-up resister OFF.
VIN = VDD
(Including OFF state leak
current of the output Tr.)
3.0 to 5.5
1
IIH(2)
IIH(3)
RES
VIN = VDD
When configured as an
input port
VIN = VDD
VIN = VDD
VIN = VBIS+0.5V
(VBIS : Bias voltage)
3.0 to 5.5
1
XT1, XT2
3.0 to 5.5
1
IIH(4)
IIH(5)
CF1
3.0 to 5.5
15
High level input
current
P87/AN7/MICIN
small signal input
3.0 to 5.5
4.2
8.5
15
IIL(1)
Port 0, 1, 3, 7, 8
Port A, B, C, D, E, F, L
Output disabled
Pull-up resister OFF.
VIN = VSS
(Including OFF state leak
current of the output Tr.)
3.0 to 5.5
-1
IIL(2)
IIL(3)
RES
VIN = VSS
When configured as an
input port
VIN = VSS
VIN = VSS
VIN = VBIS-0.5V
(VBIS : Bias voltage)
3.0 to 5.5
-1
XT1, XT2
3.0 to 5.5
-1
IIL(4)
IIL(5)
CF1
3.0 to 5.5
-15
Low level input
current
P87/AN7/MICIN
small signal input
3.0 to 5.5
-15
-8.5
-4.2
μ
A
VOH(1)
VOH(2)
VOH(3)
VOH(4)
VOH(5)
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
VODLS
IOH = -1.0mA
IOH = -0.1mA
IOH = -0.4mA
IOH = -1.0mA
IOH = -0.1mA
IOL = 10mA
IOL = 1.6mA
IOL = 30mA
IOL = 1mA
IOL = 0.5mA
IOL = 8mA
IOL = 1.4mA
IO = 0mA
VLCD, 2/3VLCD, 1/3VLCD
level output Refer to figure 8
4.5 to 5.5
VDD-1
VDD-0.5
VDD-1
VDD-1
VDD-0.5
Port 0, 1, 3, CMOS
output option
3.0 to 5.5
Port 7
3.0 to 5.5
4.5 to 5.5
High level output
voltage
Port A, B, C, D, E, F
3.0 to 5.5
4.5 to 5.5
1.5
Port 0, 1, 3
3.0 to 5.5
0.4
Port 30, 31
4.5 to 5.5
1.5
4.5 to 5.5
0.4
Port 7, 8
3.0 to 5.5
0.4
4.5 to 5.5
1.5
Low level output
voltage
Port A, B, C, D, E, F
3.0 to 5.5
0.4
S0 to S47
3.0 to 5.5
0
± 0.2
LCD output
voltage regulation
VODLC
COM0 to COM3
IO = 0mA
VLCD, 2/3VLCD, 1/2VLCD
1/3VLCD level output
Refer to figure 8
3.0 to 5.5
0
± 0.2
V
RLCD(1)
Resistance per one bias
resistor
Refer to figure 8
3.0 to 5.5
60
LCD bias resistor
RLCD(2)
Resistance per one
bias resistor
1/2R mode
Refer to figure 8
3.0 to 5.5
30
4.5 to 5.5
15
40
70
Resistance of
pull-up MOS Tr.
Rpu
Port 0, 1, 3, 7
Port A, B, C, D, E, F
VOH = 0.9VDD
3.0 to 5.5
25
70
150
k
VHIS(1)
Port 1, 7
RES
Port 87 small signal
input
3.0 to 5.5
0.1VDD
Hysterisis voltage
VHIS(2)
3.0 to 5.5
0.1VDD
V
Continued on next page.