參數(shù)資料
型號: LC87F74C8A
廠商: Sanyo Electric Co.,Ltd.
英文描述: 8-bit 1-chip Microcontroller
中文描述: 8位1片上微控制器
文件頁數(shù): 13/21頁
文件大?。?/td> 575K
代理商: LC87F74C8A
LC87F74C8A
No.7825-13/21
Continued from preceding page.
Limits
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
Pin capacitance
CP
All pins
All other terminals
connected to VSS.
f = 1MHz
Ta = 25°C
3.0 to 5.5
10
pF
Input sensitivity
Vsen
Port 87 small signal
input
3.0 to 5.5
0.12VDD
Vp-p
Serial Input/Output Characteristics
/ Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Limits
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
Cycle time
tSCK(1)
4/3
tSCKL(1)
2/3
Low level pulse
width
tSCKLA(1)
2/3
tSCKH(1)
2/3
High level pulse
width
tSCKHA(1)
SCK0 (P12)
Refer to figure 6
3.0 to 5.5
3
Cycle time
tSCK(2)
2
Low level pulse
width
tSCKL(2)
1
I
High level pulse
width
tSCKH(2)
SCK1 (P15)
Refer to figure 6
3.0 to 5.5
1
Cycle time
tSCK(3)
4/3
tCYC
tSCKL(3)
1/2
Low level pulse
width
tSCKLA(2)
3/4
tSCKH(3)
1/2
High level pulse
width
tSCKHA(2)
SCK0 (P12)
CMOS output
Refer to figure 6
3.0 to 5.5
2
tSCK
Cycle time
tSCK(4)
2
tCYC
Low level pulse
width
tSCKL(4)
1/2
S
O
High level pulse
width
tSCKH(4)
SCK1 (P15)
CMOS output
Refer to figure 6
3.0 to 5.5
1/2
tSCK
4.5 to 5.5
0.03
Data set-up time
tsDI
3.0 to 5.5
0.1
4.5 to 5.5
0.03
S
Data hold time
thDI
SI0 (P11),
SI1 (P14),
SB0 (P11),
SB1 (P14)
Measured with respect to
SI0CLK leading edge.
Refer to figure 6
3.0 to 5.5
0.1
4.5 to 5.5
1/3 tCYC
+0.05
S
Output delay time
tdDO
SO0 (P10),
SO1 (P13),
SB0 (011),
SB1 (P14)
When Port is open drain :
Time delay form SIOCLK
trailing edge to the SO
data change
Refer to figure 6
3.0 to 5.5
1/3 tCYC
+0.25
μ
s
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