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參數(shù)資料
| 型號： | LC87F57C8A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8 BIT SINGLE CHIP MICROCONTROLLER |
| 中文描述： | 8位單片機(jī) |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 336K |
| 代理商： | LC87F57C8A |
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LC87F57C8A
Ver.1.00
3/27
(8) AD converter
- 12-channel × 8-bit AD converter
(9) PWM
- 2 channel × synchronous variable 12 bit PWM
(10) Parallel interface
- RS, RD , WR , CS0 outputs (polarity can be toggled)
- read/write possible in 1 T
CYC
(11) Remote receiver circuit (share with P73/INT3/T0IN terminal)
- Noise rejection function (The filtering time of the noise rejection filter (1T
CYC
/32 T
CYC
/128 T
CYC
) can be
switched by program.)
(12) Watchdog timer
- External RC circuit is required.
- Interrupt or system reset is activated when the timer overflows.
(13) Interrupts
- 20-source and 10-vectored interrupt function:
1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level
nesting possible. During interrupt handling, an equal or lower level interrupt request is refused.
2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt
takes precedence. In the case of equal priority levels, the vector with the lowest address takes
precedence.
No.
Vector
Selectable
Level
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/Base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
Priority Level: X > H > L
For equal priority levels, vector with lowest address takes precedence.
(14) Subroutine stack levels
- A maximum of 1536 levels (set stack inside RAM)
(15) Multiplication and division
- 16 bits × 8 bits (5 instruction-cycle times)
- 24 bits × 16 bits (12 instruction-cycle times)
- 16 bits ÷ 8 bits (8 instruction-cycle times)
- 24 bits ÷ 16 bits (12 instruction-cycle times)
(16) Oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- CF oscillation circuit used for the system clock
- Crystal oscillation circuit used for the system clock
- Built-in frequency variable RC oscillation circuit used for the system clock
(17) System clock divider
- operable on the lowest power consumption
- Minimum instruction cycle time (300ns, 600ns, 1.2μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs can be
switched by program (when using 10MHz main clock)
Interrupt signal
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