參數(shù)資料
型號： LC87F57C8A
廠商： Sanyo Electric Co.,Ltd.
英文描述： 8 BIT SINGLE CHIP MICROCONTROLLER
中文描述： 8位單片機
文件頁數(shù)： 19/28頁
文件大?。?/td> 336K
代理商： LC87F57C8A
LC87F57C8A
Ver.1.00
19/27
Limits
min.
Parameter
Symbol
Pins
Conditions
VDD[V]
2.5 - 5.5 1/6tCYC
typ.
1/6
tCYC
1/3
tCYC
1/3
tCYC
1/2
tCYC
max.
unit
tCYC
& ns
tRDH(1)
RD
(PA4)
-5ns
RD
’H’ pulse width
tRDH(2)
RD
(PA4)
2.5 - 5.5 1/3tCYC
-5ns
tRDL(1)
RD
(PA4)
2.5 - 5.5 1/3tCYC
-5ns
RD
’L’ pulse width
tRDL(2)
RD
(PA4)
2.5 - 5.5 1/2tCYC
-5ns
tdDT(1)
RD
(PA4), PB0-PB7
2.5 - 5.5
1/6tCYC
-15ns
Data write
maximum delay
tdDT(2)
RD
(PA4), PB0-PB7
The time delay
allowed, from
RD
leading edge until
input data set-up
(Note 1)
2.5 - 5.5
1/3tCYC
-15ns
Input data
set-up time
tsDTR(1)
RD
(PA4), PB0-PB7 From input data set-
up to
RD
leading
edge.
(Note 2)
2.5 - 5.5
40
ns
Input data
hold time
thDTR(1)
RD
(PA4), PB0-PB7 From
RD
leading
edge until input data
hold
From output data set-
up until
WR
leading edge
2.5 - 5.5
0
ns
tsDTW(1)
RD
(PA4), PB0-PB7
2.5 - 5.5 1/3tCYC
-30ns
Output data
set-up time
tsDTW(2)
RD
(PA4), PB0-PB7
2.5 - 5.5 1/3tCYC
-30ns
0
tCYC
& ns
thDTW(1)
2.5 - 5.5
Output data
hold time
thDTW(2)
RD
(PA4), PB0-PB7 From
WR
leading
edge until output data
hold
2.5 - 5.5
0
ns
Note 1 : Time until incorrect data of Low disappears.
Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1).
6. Pulse input conditions / Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V
Limits
min.
Parameter
Symbol
Pins
Conditions
VDD[V
]
2.5 - 5.5
typ.
max.
unit
tPIH(1)
tPIL(1)
INT0(P70),
INT1(P71),
INT2(P72)
INT4(P20-P23)
INT5(P24-P27)
INT3(P73)
(The noise rejection clock
is selected to 1/1.)
INT3(P73)
(The noise rejection clock
is selected to 1/32.)
Interrupt acceptable
Timer 0 and 1 event
input acceptable
1
tPIH(2)
tPIL(2)
Interrupt acceptable
Timer 0 event input
acceptable
Interrupt acceptable
Timer 0 event input
acceptable
Interrupt acceptable
Timer 0 event input
acceptable
Reset acceptable
2.5 - 5.5
2
tPIH(3)
tPIL(3)
2.5 - 5.5
64
tPIH(4)
tPIL(4)
INT3(P73)
(The noise rejection clock
is selected to 1/128.)
RES
2.5 - 5.5
256
t
CYC
High/low level
pulse width
tPIL(5)
2.5 - 5.5
200
μs
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