參數(shù)資料
型號(hào)： LC72714
廠商： Sanyo Electric Co.,Ltd.
英文描述： Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
中文描述： 多重移動(dòng)調(diào)頻廣播集成電路片VICS解碼器
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 232K
代理商： LC72714
No. 6871-3/29
LC72714W
Allowable Operating Ranges: Parallel Interface
at Ta = –40 to +85°C, V
SS
= 0 V
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 280 ns (minimum).
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Address to RD setup
t
SARD
t
HARD
t
WRDL
1
t
WRDL
2
t
CYRD
t
WRDY
t
RDH
t
SAWR
t
HAWR
t
CYWR
t
WWRL
t
WDH
t
DRDY
A0/CL, A1/CE, A2/DI, A3, RD
20
ns
RD to address hold
A0/CL, A1/CE, A2/DI, A3, RD, t
WRDL
=>250 ns
RD
–20
ns
RD low-level width
280
ns
RD low-level width (when RDY is used)
RD
100
280
ns
RD cycle wait
A0/CL, A1/CE, A2/DI, A3, RD
150
ns
RDY width (Register read)
RDY
60
230
ns
RD data hold
RD, DATn
0
ns
Address to WR setup
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR to address hold
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR cycle wait
A0/CL, A1/CE, A2/DI, A3, WR
150
ns
WR low-level width
WR
200
ns
WR data hold
WR, DATn
0
ns
RDY output delay
RD, RDY
0
50
ns
Corrected output RD width
t
WDRD
1
RD (BUSWD = L 8 bits)
300
ns
RD (BUSWD = H 16 bits)
540
ns
Corrected output RD width
t
WDRD
2
RD (BUSWD = L 8 bits)
100
300
ns
(when RDY is used)
RD (BUSWD = H 16 bits)
300
540
ns
RDY width (corrected output read)
t
WDRDY
RDY (BUSWD = L 8 bits)
60
230
ns
RDY ((BUSWD = H 16 bits)
300
490
ns
DACK to DREQ delay
t
DREQ
t
CYDM
t
WRDM
DREQ, DACK
260
ns
DMA cycle wait
RD, DREQ
420
ns
RD low-level width (DMA)
RD
300
ns
P
Electrical Characteristics
at V
DD
= +2.7 to +3.6 V, within the allowable operating ranges
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
OH
1
Io = 1 mA, BCK, FCK, BLOCK, FLOCK,
CRC4, CLK16DATA
V
DD
– 0.4
V
High-level output voltage
V
OH
2
V
OL
1
V
OL
2
V
OL
3
Io = 2 mA, INT, RDY, DREQ, D0 to D15
V
DD
– 0.4
V
Io = 1 mA, Pins for which V
OH
1 applies
Io = 2 mA, Pins for which V
OH
2 applies
Io = 1 mA, DO, INT
0.4
V
Low-level output voltage
0.4
V
0.4
V
I
IH
1
V
IN
= 5.5 V, A0/CL, A1/CE, A2/DI, RST,
STNBY
1.0
μA
High-level input current
I
IH
2
I
IL
Rmpx
V
IN
= V
DDD
, All input pins other than I
IH
1
V
IN
= V
SSD
, All input pins
MP
XIN
– Vssa f = 100 kHz
Vref, Vdda = 3 V
1.0
μA
Low-level input current
–1.0
μA
k
V
Input resistance
50
Reference supply voltage output
Vref
1.5
Bandpass filter center frequency
Fc
FLOUT
76.0
kHz
–3 dB bandwidth
Fbw
FLOUT
19.0
kHz
Group delay
Dgd
FLOUT
–7.5
+7.5
μs
Gain
Gain
FLOUT – MPXIN f = 76 kHz
20
dB
ATT1
FLOUT f = 50 kHz
25
dB
Stop band attenuation
ATT2
FLOUT f = 100 kHz
15
dB
ATT3
FLOUT f = 30 kHz
50
dB
ATT4
FLOUT f = 150 kHz
50
dB
Output off leakage current
IOFF
V0 = V
DDD
, DO
A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,
DACK, IOCNT1, IOCNT2, RST, STNBY
1.0
μA
Hysteresis voltage
VHIS
0.1 V
DDD
V
Internal feedback resistor
Rf
XIN, XOUT
1.0
M
mA
Current drain
I
DD
12
20
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