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參數(shù)資料
| 型號(hào)： | LC72349G |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Low-Voltage ETR Controller with On-Chip LCD Driver |
| 中文描述： | 低電壓東突控制器的片上LCD驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 119K |
| 代理商： | LC72349G |
No. 6472-13/14
LC72348G/W, 72349G/W
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
SS
SWR
N
Set status register
(Status W-reg) N
←
1
(Status W-reg) N
←
0
if (Status R-reg) N = all
RS
SWR
N
Reset status register
TST
SRR
N
Test status register true
TSF
SRR
N
Test status register false
if (Status R-reg) N = all
TUL
N
Test Unlock F/F
if Unlock F/F (N) = all 0s,
then skip
PLL reg
←
PLL data
UCCW1
←
I
UCCW2
←
I
BEEP reg
←
I
DZC reg
←
I
Timer reg
←
I
IOS reg PWn
←
N
M
←
(Pn)
P1n
←
M
M
←
(Pn)
(Pn)N
←
1
(Pn)N
←
0
PLL
M
Load M to PLL register
UCS
I
Set I to UCCW1
UCC
I
Set I to UCCW2
BEEP
I
Beep control
DZC
I
Dead zone control
TMS
I
Set timer register
IOS
PWn
N
Set port control word
IN
M
Pn
Input port data to M
OUT
M
Pn
Output contents of M to port
INR
M
Pn
Input port data to M
SPB
P1n
N
Set port1 bits
RPB
P1n
N
Reset port1 bits
TPT
P1n
N
Test port1 bits, then skip if all bits if (Pn)N = all 1s, then skip
TPF
P1n
N
Test port1 bits, then skip if all bits if (Pn)N = all 0s, then skip
BANK
I
Select Bank
BANK
←
I
LCDA
M
I
Output segment pattern to LCD
digit direct
LCD (DIGIT)
←
M
LCDB
M
I
LCPA
M
I
Output segment pattern to LCD
digit through LA
LCD (DIGIT)
←
LA
←
M
LCPB
M
I
HALT
I
Halt mode control
HALT reg
←
I,
then CPU clock stop
CKSTP
Clock stop
Stop x’tal OSC
NOP
No operation
No operation
f
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
SWR
N
1
1
1
1
1
1
1
1
0
0
1
SWR
N
1
1
1
1
1
1
1
1
0
1
SRR
N
1
1
1
1
1
1
1
1
1
0
SRR
N
0
0
0
0
0
0
0
0
1
1
0
1
N
1
1
1
1
1
0
DH
DL
r
0
0
0
0
0
0
0
0
0
0
0
1
I
0
0
0
0
0
0
0
0
0
0
1
0
I
0
0
0
0
0
0
0
0
0
1
1
0
I
0
0
0
0
0
0
0
0
1
0
1
1
I
0
0
0
0
0
0
0
0
1
1
0
0
I
1
1
1
1
1
1
1
0
PWn
N
1
1
1
0
1
0
DH
DL
Pn
1
1
1
0
1
1
DH
DL
Pn
0
0
1
1
1
0
DH
DL
Pn
0
0
0
0
0
0
1
0
Pn
N
0
0
0
0
0
0
1
1
Pn
N
1
1
1
1
1
1
0
0
Pn
N
1
1
1
1
1
1
0
1
Pn
N
0
0
0
0
0
0
0
0
0
1
1
1
I
1
1
0
0
0
0
DH
DL
DIGIT
1
1
0
0
0
1
DH
DL
DIGIT
1
1
0
0
1
0
DH
DL
DIGIT
1
1
0
0
1
1
DH
DL
DIGIT
0
0
0
0
0
0
0
0
0
1
0
0
I
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
B
i
S
i
H
i
L
i
O
i
I
Instruc-
tions
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