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參數(shù)資料
| 型號(hào)： | LC72349G |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Low-Voltage ETR Controller with On-Chip LCD Driver |
| 中文描述： | 低電壓東突控制器的片上LCD驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | LC72349G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)
No. 6472-12/14
LC72348G/W, 72349G/W
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
SEQ
r
M
Skip if r equal to M
(r) – (M), skip if zero
SEQI
M
I
Skip if M equal to I
(M) – I, skip if zero
SNEI
M
I
Skip if M not equal to I
(M) – I, skip if not zero
SGE
r
M
Skip if r is greater than or
equal to M
(r) – (M),
skip if not borrow
SGEI
M
I
Skip if M is greater than
equal to I
(M) – I, skip if not borrow
SLEI
M
I
Skip if M is less than I
(M) – I, skip if borrow
r
←
(r) AND (M)
M
←
(M) AND I
r
←
(r) OR (M)
M
←
(M) OR I
r
←
(r) XOR (M)
M
←
(M) XOR I
carry
(r)
AND
r
M
AND M with r
ANDI
M
I
AND I with M
OR
r
M
OR M with r
ORI
M
I
OR I with M
EXL
r
M
Exclusive OR M with r
EXLI
M
I
Exclusive OR M with M
SHR
r
Shift r right with carry
LD
r
M
Load M to r
r
←
(M)
M
←
(r)
ST
M
r
Store r to M
MVRD
r
M
Move M to destination M
referring to r in the same row
[DH, Rn]
←
(M)
MVRS
M
r
Move source M referring to r
to M in the same row
M
←
[DH, Rn]
MVSR
M1
M2
Move M to M in the same row
[DH, DL1]
←
[DH, DL2]
M
←
I
MVI
M
I
Move I to M
TMT
M
N
Test M bits, then skip if all bits
specified are true
if M (N) = all 1s, then skip
TMF
M
N
Test M bits, then skip if all bits
specified are false
if M (N) = all 0s, then skip
JMP
ADDR
Jump to the address
PC
←
ADDR
PC
←
ADDR
Stack
←
(PC) + 1
PC
←
Stack
PC
←
Stack,
BANK
←
Stack,
CARRY
←
Stack
CAL
ADDR
Call subroutine
RT
Return from subroutine
RTI
Return from interrupt
f
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
DH
DL
r
0
0
0
1
0
1
DH
DL
I
0
0
0
0
0
1
DH
DL
I
0
0
0
1
1
0
DH
DL
r
0
0
0
1
1
1
DH
DL
I
0
0
0
0
1
1
DH
DL
I
0
0
1
0
0
0
DH
DL
r
0
0
1
0
0
1
DH
DL
I
0
0
1
0
1
0
DH
DL
r
0
0
1
0
1
1
DH
DL
I
0
0
1
1
0
0
DH
DL
r
0
0
1
1
0
1
DH
DL
I
0
0
0
0
0
0
0
0
1
1
1
0
r
1
1
0
1
0
0
DH
DL
r
1
1
0
1
0
1
DH
DL
r
1
1
0
1
1
0
DH
DL
r
1
1
0
1
1
1
DH
DL
r
1
1
1
0
0
0
DH
DL1
DL2
1
1
1
0
0
1
DH
DL
I
1
1
1
1
0
0
DH
DL
N
1
1
1
1
0
1
DH
DL
N
1
0
0
ADDR (13 bits)
1
0
1
ADDR (13 bits)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
B
i
J
c
C
L
T
Continued on next page.
Instruc-
tions
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