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參數(shù)資料
| 型號(hào)： | LC72137M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | MFP20 |
| 文件頁(yè)數(shù)： | 9/22頁(yè) |
| 文件大?。?/td> | 348K |
| 代理商： | LC72137M |
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Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock
determination requires a time longer than the period of the reference frequency. However, immediately after changing
the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference
frequency.
No. 5743-17/22
LC72137, 72137M
Figure 1 Unlock Detection Timing
For example, if fref is 1 kHz (and thus the period is 1 ms), after changing the divisor N, the system must wait at least
2 ms before checking for the unlocked state.
Figure 2 Circuit Structure
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