參數(shù)資料
型號: LC72137M
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: MFP20
文件頁數(shù): 11/22頁
文件大?。?/td> 348K
代理商: LC72137M
No. 5743-19/22
LC72137, 72137M
When directly outputting data from the DO pin (set up by the DO pin control data)
Since the DO pin outputs the unlocked state (locked: high, unlocked: low) the timing considerations in the technique
described in the previous section are not necessary. After changing the value of N, the locked state can be determined
after waiting at least two periods of the reference frequency.
Notes on Clock Time Base Usage
When the clock time base output is used, the value of the pull-up resistor for the output pin (BO1) must be at least 100 k
.
We recommend the use of a Schmitt input on the receiving controller (microprocessor) to prevent chattering.This is to
avoid degradation of the VCO C/N characteristics when using the built-in low-pass filter transistor to form the loop
filter. Since the clock time base output pin and the low-pass filter transistor ground are the same mode in the IC, the time
base output pin current fluctuations must be suppressed to limit the influence on the low-pass filter.
Other Items
1. Notes on the Phase Comparator Dead Zone
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.
The following problems may occur in the ON/ON state.
Side band generation due to reference frequency leakage
Side band generation due to both the correction pulse envelope and low frequency leakage
DZ1
DZ0
Dead-zone mode
Charge pump
Dead zone
0
DZA
ON/ON
– –0 s
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
DZD
OFF/OFF
+ +0 s
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LC72137 PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP22
LC72137M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
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