LC573104A, 573102A
No.4144–15/16
Continued from preceding page.
I
B
C
Mnemonic
Instruction code
Function
Status
flag
affected
Function description
B
M
JMP X
0 0 0 0
X7X6X5X4
0 1 0 0
X7X6X5X4
0 1 0 1
X7X6X5X4
0 1 1 0
X7X6X5X4
0 1 1 1
X7X6X5X4
0 1 0 0
X7X6X5X4
0 1 0 1
X7X6X5X4
0 1 1 0
X7X6X5X4
0 1 1 1
X7X6X5X4
0 0 0 1
1 X10X9X8
X3X2X1X0
1 X10X9X8
X3X2X1X0
1 X10X9X8
X3X2X1X0
1 X10X9X8
X3X2X1X0
1 X10X9X8
X3X2X1X0
0 X10X9X8
X3X2X1X0
0 X10X9X8
X3X2X1X0
0 X10X9X8
X3X2X1X0
0 X10X9X8
X3X2X1X0
0 0 0 1
(PC10 to PC0)
←
X10 to X0
2
2
Loads data specified by X10 to X0 to PC and jumps unconditionally.
BAB0 X
If AC0=1 then
(PC10 to PC0)
←
X10 to X0
If AC1=1 then
(PC10 to PC0)
←
X10 to X0
If AC2=1 then
(PC10 to PC0)
←
X10 to X0
If AC3=1 then
(PC10 to PC0)
←
X10 to X0
If AC
=0
then
(PC10 to PC0)
←
X10 to X0
If AC
≠
0 then
(PC10 to PC0)
←
X10 to X0
If CF
≠
1 then
(PC10 to PC0)
←
X10 to X0
If CF=1 then
(PC10 to PC0)
←
X10 to X0
PAGE
←
[M (DP)]
2
2
When AC bit 0 is '1', data specified by X10 to X0 is loaded to PC and jumps.
At '0', PC is incremented +2.
BAB1 X
2
2
When AC bit 1 is '1', data specified by X10 to X0 is loaded to PC and jumps.
At '0', PC is incremented +2.
BAB2 X
2
2
When AC bit 2 is '1', data specified by X10 to X0 is loaded to PC and jumps.
At '0', PC is incremented +2.
BAB3 X
2
2
When AC bit 3 is '1', data specified by X10 to X0 is loaded to PC and jumps.
At '0', PC is incremented +2.
BAZ X
2
2
When AC is '0', data specified by X10 to X0 is loaded to PC and jumps.
When AC is not '0', PC is incremented +2.
BANZ X
2
2
When AC is not '0', data specified by X10 to X0 is loaded to PC and jumps.
When AC is '0', PC is incremented +2.
BCNH X
2
2
When CF is '0', data specified by X10 to X0 is loaded to PC and jumps.
When CF is '1', PC is incremented +2.
BCH X
2
2
When CF is '1', data specified by X10 to X0 is loaded to PC and jumps.
When CF is '0', PC is incremented +2.
PAGE
1
1
Memory M (DP) contents loaded to PAGE latch.
JMP*
0 0 0 1
0 0 0 0
PC10 to PC08
←
(PAGE)
PC07 to PC04
←
(AC)
PC03 to PC00
←
[M (DP)]
PC11
←
0
1
1
Unconditionally jumps to page specified by PAGE and address whose low-
order 8 bits are specified by contents of AC and memory M (DP).
SPC1
1 1 0 0
0 0 1 0
1 0 0 1
0 0 0 1
SPC
←
1
2
2
Sets strobe pointer control bit (SPC) to '1'.
JSR X
1 0 1 0
X7X6X5X4
0 0 0 1
0 X10X9X8
X3X2X1X0
0 0 1 1
STACK
←
(PC)+2
(PC10 to PC0)
←
X10 to X0
PC
←
(STACK)
2
2
Current PC+2 contents are saved in STACK, data specified by X10 to X0 is
loaded to PC and sub-routine is called.
ROM0
1 1 0 0
0 0 1 0
1 0 0 0
0 0 0 0
2
2
Select ROM bank 0.
SCF0
SCF4
SPC
SPC
CSEC
1 1 1 1
1 0 1 1
φ
11 to
φ
15
←
0
1
1
Resets high-order 4 bits of divider circuit.
RWDT
1 1 1 1
1 0 0 1
(WDT)
←
0
1
1
Resets Watchdog Timer counter.
RST
1
1
Returns PC contents saved in STACK to PC and returns from sub-routine.
SPC0
1 1 0 0
0 0 1 0
1 0 0 1
0 0 0 0
SPC
←
0
2
2
Resets strobe pointer control bit (SPC) to '0'.
ROM1
1 1 0 0
0 0 1 0
1 0 0 0
0 0 0 1
PC11
←
1
2
2
Select ROM bank 1.