參數(shù)資料
型號(hào)： LC573102A
廠商： Sanyo Electric Co.,Ltd.
英文描述： 4-bit Single Chip Microcontroller
中文描述： 4位單片微控制器
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 181K
代理商： LC573102A
LC573104A, 573102A
No.4144–12/16
LC573100 Series Instructions
I
B
C
Mnemonic
Instruction code
Function
Status
flag
affected
CF
CF
Function description
A
L
A
TAAT
0 0 0 0
0 0 0 1
AC, TRGE
←
ROM
1
2
Contents of ROM on current page, addressed by PC whose low-orderd 8 bits
are replaced with contents of AC and M (DP), are loaded to AC and TREG
MTR
0 0 0 1
0 0 1 0
M (DP)
←
TREG
1
1
Stores the conternts of TREG memory location pointed to by DP.
ASR0
0 0 0 1
1 0 0 0
ACn
←
ACn+1, AC3
←
0
1
1
Shifts the contents of the AC right and enter 0 into the MSB.
ASR1
0 0 0 1
1 0 0 1
ACn
←
ACn+1, AC3
←
1
1
1
Shifts the contents of the AC right and enter 1 into the MSB.
ASL0
0 0 0 1
1 0 1 0
ACn
←
ACn–1, AC0
←
0
1
1
Shifts the contents of the AC left and enter 0 into the LSB.
ASL1
0 0 0 1
1 0 1 1
ACn
←
ACn–1, AC0
←
1
1
1
Shifts the contents of the AC left and enter 1 into the LSB.
INC
1 0 0 1
1 0 0 0
AC, M (DP)
←
M (DP)+1
1
1
Memory M (DP) contents incremented +1, and loaded to AC and M (DP).
DEC
1 0 0 1
1 0 0 1
AC, M (DP)
←
M (DP)–1
1
1
Memory M (DP) contents decremented –1, and loaded to AC and M (DP).
ADC
1 0 0 0
0 0 0 0
AC
←
(AC)+[M (DP)]+CF
1
1
AC, memory M (DP) and CF contents are binary-added and the result loaded
to AC.
ADC*
1 0 0 0
1 0 0 0
AC, M (DP)
←
(AC)+[M (DP)]+CF
1
1
AC, memory M (DP) and CF contents are binary-added and the result loaded
to AC, M (DP).
CF
ADCI X
1 0 0 1
– – – –
0 0 0 0
X3X2X1X0
0 0 0 1
AC
←
(AC)+X+CF
2
2
AC, immediate data and CF contents are binary-added, and the result loaded
to AC.
CF
ADDI X
1 0 0 1
– – – –
0 0 1 0
X3X2X1X0
0 0 1 1
AC
←
(AC)+X
2
2
AC and immediate data contents are binary-added and the result loaded to
AC.
ADNI X
1 0 0 1
– – – –
0 1 0 0
X3X2X1X0
0 1 0 1
AC
←
(AC)+X
2
2
AC and immediate data contents are binary-added and the result loaded in AC.
ANDI X
1 0 0 1
– – – –
0 1 0 1
X3X2X1X0
0 1 1 0
AC
←
(AC) X
2
2
AC and immediate data contents are ANDed and the result loaded to AC.
EORI X
1 0 0 1
– – – –
0 1 1 0
X3X2X1X0
0 1 1 1
AC
←
(AC)
∨
X
2
2
AC and immediate data are exclusive ORed and the result loaded to AC.
ORI X
1 0 0 1
– – – –
0 1 1 1
X3X2X1X0
AC
←
(AC)
∨
X
2
2
AC and immediate data are ORed and the result loaded to AC.
CF
SBCI X
1 0 0 1
– – – –
0 0 0 1
X3X2X1X0
0 0 1 0
AC
←
(AC)+X+CF
2
2
AC, immediate data and CF contents are binary-subtracted and the result
loaded to AC.
CF
SUBI X
1 0 0 1
– – – –
0 0 1 1
X3X2X1X0
0 1 0 0
AC
←
(AC)+X+1
2
2
AC and immediate data contents are binary-subtracted and the result loaded in
AC.
CF
CF
SBC
1 0 0 0
AC
←
(AC)+[M (DP)]+CF
1
1
AC, memory M (DP) and CF contents are binary-subtracted, and the result
loaded to AC.
CF
SUB
1 0 0 0
AC
←
(AC)+[M (DP)]+1
1
1
AC and memory M (DP) contents are binary-subtracted and the result loaded
to AC.
CF
SUB*
1 0 0 0
1 0 1 1
AC, M (DP)
←
(AC)+[M (DP)]+1
1
1
AC and memory M (DP) contents are binary-subtracted and the result loaded
to AC and M (DP).
CF
ADD
1 0 0 0
AC
←
(AC)+[M (DP)]
1
1
AC and memory M (DP) contents are binary-added and the result loaded to
AC.
ADN
1 0 0 0
AC
←
(AC)+[M (DP)]
1
1
AC and memory M (DP) contents are binary-added and the result loaded to
AC.
AND
1 0 0 0
AC
←
(AC) [M (DP)]
1
1
AC and memory M (DP) contents are ANDed and the result loaded to AC.
ADN*
1 0 0 0
1 1 0 0
AC, M (DP)
←
(AC)+[M (DP)]
1
1
AC and memory M (DP) contents are binary-added and the result loaded to
AC and M (DP).
CF
ADD*
1 0 0 0
1 0 1 0
AC, M (DP)
←
(AC)+[M (DP)]
1
1
AC and memory M (DP) contents are binary-added and the result loaded to
AC and M (DP).
SBC*
1 0 0 0
1 0 0 1
AC, M (DP)
←
(AC)+[M (DP)]+CF
1
1
AC, memory M (DP) and CF contents are binary-subtracted, and the result
loaded to AC and M (DP).
EOR
1 0 0 0
AC
←
(AC)
∨
[M (DP)]
1
1
AC and memory M (DP) are exclusive ORed and the result loaded to AC.
OR
1 0 0 0
AC
←
(AC)
∨
[M (DP)]
1
1
AC and memory M (DP) are ORed and the result loaded to AC.
OR*
1 0 0 0
1 1 1 1
AC, M (DP)
←
(AC)
∨
[M (DP)]
1
1
AC and memory M (DP) are ORed and the result loaded to AC and M (DP).
EOR*
1 0 0 0
1 1 1 0
AC, M (DP)
←
(AC)
∨
[M (DP)]
1
1
AC and memory M (DP) are exclusive ORed, and the result loaded to AC and
M (DP).
AND*
1 0 0 0
1 1 0 1
AC, M (DP)
←
(AC) [M (DP)]
1
1
AC and memory M (DP) contents are ANDed and the result loaded to AC and
M (DP).
Continued on next page.
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參數(shù)描述
LC573104A 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4-bit Single Chip Microcontroller
LC5732 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4-Bit Microcomputer with LCD Driver
LC573202A 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4-Bit Microcontroller with 2K-Byte ROM, 64 】 4Bits RAM and LCD Driver
LC5732H 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4-Bit Microcomputer with LCD Driver
LC5732N 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4-Bit Microcomputer with LCD Driver
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