LC573104A, 573102A
No.4144–14/16
Continued from preceding page.
I
B
C
Mnemonic
Instruction code
Function
Status
flag
affected
Function description
C
I
HALT
0 0 0 0
0 0 0 0
CPU operation halts
1
1
Halts CPU operation. HALT mode is released under the following conditions.
HALT mode is cancelled by the interaction of SIC X and SC5 commands.
SCI X
1 1 0 1
X3X2X1X0CTL2
←
X
1
1
X0 to X3
Operation.
X0
HFE1 is set to enable release of HALT mode by overflow signal
from divider circuit following CF oscillation circuit.
X1
HFE2 is set enabling signal rise at input port S to release HALT
mode.
X2
HFE3 is set enabling signal rise at input port M to release HALT
mode.
X3
HFE4 is set enabling 1/10 second pulse to release HALT.
NOP
1 1 1 1
1 1 1 1
No operation
1
1
No operation.
IPS
1 0 1 0
1 1 1 1
AC
←
[P (S)]
1
1
Input data at input port S loaded to AC.
IPM
1 0 1 0
1 0 0 0
AC
←
[P (M)]
1
1
Input data at input port M loaded to AC.
SPDR X
1 1 1 1
0 1 X1X0
PDF
←
X
1
1
Pull-down resister MOS-Tr at corresponding input port turned ON/OFF.
X0=0
S-Terminal Pull down Tr OFF.
Bit content
Operation
(3) When SPC=1 SFR
←
(AC)
AC contents transferred to special function register SFR.
(3) When SPC=1 AC
←
(SFR)
Special function register SFR contents transferred to AC.
X1=1
M-Terminal Pull down Tr ON.
(3) When SPC=1 SFR
←
ROM
High-order 4 bits or 8 bits data of ROM, on the current page, addressed by PC
whose low-order 8 bits are replaced by AC and M (DP) contents is transferred
to special function register SFR
X0=1
S-Terminal Pull down Tr ON.
CFCF
CCF
CFCF
CCF
PDF
HEF1 to
HEF4
TWRT
0 0 0 0
0 0 1 0
(1) Cannot be used when SPC
=0&SP=0H to CH, EH, FH.
1
1
Cannnot be used. (Causes error when TWRT is executed at SPC=0&SP=0H to
CH, EH, FH.)
(2) When SPC=0&SP=D
CTL3
←
ROM
High-order 4 bits data of ROM, on current page, addressed by PC whose low-
order 8 bits are replaced by AC and M (DP) contents, is transferred to CTL3.
OUT
1 1 1 1
1 1 0 0
(1) Cannot be used when SPC
=0&SP=0H to CH, EH, FH.
1
1
Cannnot be used. (Causes error when OUT is executed at SPC=0&SP=0H to
CH, EH, FH.)
IN
0 0 0 1
0 1 1 1
(1) Cannot be used at SPC
=0&SP=0H to CH, EH, FH.
1
1
Cannnot be used. (Causes error when IN is executed at SPC=0&SP=0H to
CH, EH, FH.)
(2) When SPC=0&SP=D
AC
←
(STS3)
STS3 contents transferred to AC.
(2) When SP=0&SP=D
CTL3
←
(AC)
AC contents transferred to CTL3.
X1=0
M-Terminal Pull down Tr OFF.
Continued on next page.