- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358754 > LC35V1000BM (Sanyo Electric Co.,Ltd.) Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | LC35V1000BM |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM |
| 中文描述： | 異步硅門100萬(wàn)（131072字× 8位）的SRAM |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | LC35V1000BM |
Notes: 1. The times t
COD1
, t
COD2
, t
OOD
, and t
WOD
are stipulated as the times until the output reaches the high-impedance
state. They are not stipulated by output voltage level.
2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state.
3. t
WP
is the period that CE1 and WE are at the low level and CE2 is at the high level, and is defined as the time
from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first.
4. t
CW1
and t
CW2
are the period that CE1 and WE are at the low level and CE2 is at the high level, and are defined
as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever
occurs first.
5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high
level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level.
6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state.
No. 7056-8/9
LC35V1000BM, BTS-70U
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Data retention supply voltage
V
DR1
V
DR2
V
CE1
≥
V
CC
– 0.2 V, V
CE2
≥
V
CC
– 0.2 V or V
CE2
≤
0.2 V
V
CE2
≤
0.2 V
V
CC
= 3.0 V, V
CE1
≥
V
CC
– 0.2 V,
V
CE2
≥
V
CC
– 0.2 V,
or V
CE2
≤
0.2 V
2.0
3.6
V
2.0
3.6
V
–40°C to +85°C
16
Data retention supply current
I
CCDR1
–40°C to +70°C
8
μA
+25°C
0.05
Chip enable setup time
t
CDR
t
R
0
ns
Chip enable hold time
5
ms
Data Retention Characteristics
at Ta = –40 to +85°C
Data Retention Waveforms (1) (CE1 control)
Note:
*
Ta = +25°C
Data retention mode
Data Retention Waveforms (2) (CE2 control)
Data retention mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC35V1000BTS-70U | Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM |
| LC35V256ET-70W | 256K (32K words x 8 bits) SRAM Control pins: OE and CE |
| LC35V256EM | 256K (32K words x 8 bits) SRAM Control pins: OE and CE |
| LC35V256EM-70W | 256K (32K words x 8 bits) SRAM Control pins: OE and CE |
| LC35W1000BM | Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC35V1000BM-70U | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述: |
| LC35V1000BTS | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述: |
| LC35V1000BTS-70U | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM |
| LC35V256EM | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:256K (32K words x 8 bits) SRAM Control pins: OE and CE |
| LC35V256EM-70W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:256K (32K words x 8 bits) SRAM Control pins: OE and CE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。