參數(shù)資料
型號： LC07410LG
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA40
封裝： 4.40 X 3.60 MM, FLGA-40
文件頁數(shù)： 5/36頁
文件大?。?/td> 367K
代理商： LC07410LG
LC07410LG
No.A1345-13/36
Specification Details
Power down/system reset
When the PDNB pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for
each block. A 0 on the PDNB pin also triggers a system reset.
After the power is first applied, the system must be reset without fail.
[See the section on “Checkpoint_2) Resetting”]
After resetting, the contents of the serial port register are initialized.
The VREF buffer is activated by releasing power down mode by setting the PDNB pin from 0 to 1, and then by setting
VREF_BIAS[1:0] to 01. When VREF_BIAS [1:0] is set to 10, VREF starts. Along with the start of VREF, the LINE
output pin is biased to 1/2VDDA. Once the VREF voltage has stabilized, VREF_BIAS [1:0] must be set to 11 (normal
state).
Reference voltage generator circuit
VREF_BIAS: Voltage Reference Bias
* Bold letters indicate initial settings.
ADRS
Bit
Name
Init
Description
01h
[5:4]
VREF_BIAS
00b
Sets the reference voltage circuit (VREF pin).
11: Normal operation (standard resistor value)
10: Quick rise to reference voltage <*1>
01: Activates IREF bias, VREF OFF 00: Power down
<*1> The target voltage is reached quickly by connecting a low-resistance element in the “reference voltage generation
circuit.” During normal operation, a standard resistance is recommended in order to save power.
Power Control
ADRS
Bit
Name
Init
Description
[7]
MIC_PDX
0b
MIC amplifier circuit, power control
1: power on
0: power down
[6]
MIC_PWR_PDX
0b
MIC power circuit (MIC_PWR pin), power control
1: power on
0: power down
[5]
PGA_PDX
0b
PGA circuit, power control
1: power on
0: power down
[4]
ADC_PDX
0b
ADC circuit, power control
1: power on
0: power down
[3]
DAC_PDX
0b
DAC circuit, power control
1: power on
0: power down
[2]
SEL_PDX
0b
Selector (LOUT2) circuit, power control
1: power on
0: power down
[1]
LO_PDX
0b
Line out circuit (LOUT1) circuit, power control
1: power on
0: power down
00h
[0]
SP_PDX
0b
Speaker amplifier circuit, power control
1: power on
0: power down
[2]
PLL_PDX
0b
PLL circuit, power control
1: power on
0: power down (PLL-EXT mode)
[1]
REG_PDX
0b
Regulator circuit, power control
1: power on
0: power down
01h
[0]
VD_PDX
0b
Video driver circuit, power control
1: power on
0: power down
Sampling Frequency Setting
Set sampling frequency used by FS [4:0] register. This is necessary to make it for correctly setting digital frequency
characteristic and ALC damping time constant. The setting is adjusted to a value that is the closest to fs used.
ADRS
Bit
Name
Init
Description
15h
[3:0]
FS
1000b
Sampling Frequency Setting
1000: 48kHz/0111: 44.1kHz/0110: 32kHz/0101: 24kHz
0100: 22.05kHz/0011: 16kHz/0010: 12kHz/0001: 11.025kHz
0000: 8kHz
Note: This setting doesn’t synchronize with PLL setting. It is necessary to set it individually respectively.
Refer to the page of PLL function explanation for PLL setting.
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