參數(shù)資料
型號(hào)： LC07410LG
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA40
封裝： 4.40 X 3.60 MM, FLGA-40
文件頁(yè)數(shù)： 16/36頁(yè)
文件大小： 367K
代理商： LC07410LG
LC07410LG
No.A1345-23/36
Playback System Automatic Level Control (ALC)
When REC_ALC is set to 0 and PB_ALC is set to 1 (playback system ALC mode), the digital volume control functions
as the playback system ALC. Subject the volume value to automatic adjustment so that the digital volume output level is
set to the predetermined value.
For further details on operation, refer to “Description of ALC/limiter (automatic level control) operation.”
Noise gate function (NGEN) setting is disabled if playback system ALC mode.
When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the digital volume control is set to manual mode,
and the gain is fixed to the EVR_GAIN [6:0] register setting.
Line Amplifier
The line amplifier provides a gain of 0dB, +4dB, +6dB or +8dB.
When LO_MUTE is set to 1, the line output is muted.
When LO_PDX is set to 0, the line amplifier is placed in the power down mode.
If the line output is set to the high-impedance state when the line amplifier is placed in the power down mode,
LO_VREFSW must be set to 0.
ADRS
Bit
Name
Init
Description
[7]
LO_MUTE
1b
Controls the mute function of the line out circuit.
1: Enables MUTE function. 0: Disables MUTE function.
[6]
LO_VREFSW
1b
State setting when power of line output id downed*
1: Connects to the reference power source (VREF).
0: Does not connect to the reference power source (VREF).
12h
[5:4]
LO_GAIN
10b
Select the gain of the line out circuit.
11: +8dB 10: +6dB 01: +4dB 00: 0dB
* It is not possible to connect between LINE OUT and VREF by setting LO_VREFSW to 1 even if LO_PDX is set to 1.
Speaker amplifier
The speaker amplifier must be started after the selector amplifier output (LOUT2) has been activated and the voltage has
stabilized. Either 0dB or +6dB can be selected as the selector amplifier gain using the SEL_GAIN setting.
VDDS in the range of 2.7V to 5.5V is supported. (Piezoelectric speaker supported)
The amplifier gain is 6dB (+12dB with the BTL output). (With an 8
Ω load)
The SPKIN input resistance is 10k
Ω (type).
When SP_PDX is set to 0, the speaker amplifier is placed in the power down mode.
Depending on VDDS, one of the four speaker terminal voltages can be selected using SP_BAIS [1:0] to achieve an
optimal dynamic range.
Thermal Shutdown
If a chip temperature of 140
°C or higher is detected while SP_TSD_EN is set 1, the speaker amplifier is placed in the
power down mode for protection.
The thermal shutdown function is disabled if SP_TSD_EN is set to 0.
ADRS
Bit
Name
Init
Description
[2]
SEL_GAIN
0b
Selector circuit, gain selection
1: +6dB 0: 0dB
12h
[1:0]
SEL_IN
01b
Selector input selection setting
00: Prohibition 01: DAC 10: ALC 11: Prohibition
[3:2]
SP_IDL
10b
Set the idling current of the speaker amplifier circuit
11: 2.0mA 10: 1.0mA 01: 0.67mA 00: 0.5mA
13h
[1:0]
SP_BIAS
00b
Set the bias control of the speaker amplifier circuit
11: 0.833
×VDDA
10: 0.766
×VDDA
01: 0.666
×VDDA
00: 0.5
×VDDA
[7]
SP_OUT_EN
0b
Enables or disables the speaker amplifier circuit
1: ON 0: OFF
14h
[6]
SP_TSD_EN
1b
Enables or disables the thermal shutdown function of the speaker amplifier circuit
1: ON 0: OFF
See the section on "Speaker Amplifier Start/Stop Sequence"
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