參數(shù)資料
型號(hào)： LAN91C95
英文描述： LAN Node Controller
中文描述： 網(wǎng)絡(luò)節(jié)點(diǎn)控制器
文件頁(yè)數(shù)： 5/55頁(yè)
文件大小： 482K
代理商： LAN91C95
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
SMSC DS – LAN91C110 REV. B
Page 5
Rev. 09/05/02
TABLE 1 - DESCRIPTION OF PIN FUNCTIONS
144 TQFP
PIN NO.
115-112,
110-100
138
NAME
SYMBOL
BUFFER
TYPE
I
DESCRIPTION
Address
A[15:1]
Input. Used by LAN91C110 for internal register
selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C110 register accesses
to determine the width of the access and the
register(s) being accessed.
Bidirectional. 16-bit data bus used to access the
LAN91C110’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering.
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete information.
Output. Local Device. This active low output is
asserted when AEN is low and A4-A15 decode to
the LAN91C110 address programmed into the
high byte of the Base Address Register. nLDEV*
is a combinatorial decode of unlatched address
and AEN signals.
Input. Address strobe. For systems that require
address latching. The rising edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1:15] and
AEN are latched.
Output. The interrupt output is enabled by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
Input. Used in asynchronous bus interfaces.
Address
Enable
AEN
I
118, 117
nBE[1:0]
I
89, 91-95,
97-98, 119,
121-123,
125-128
135
Data Bus D[15:0]
I/O8
Reset
RESET
IS
129
Asynchro-
nous
Ready
ARDY
OD16
120
Local
Device
nLDEV
O16
88
nAddress
Strobe
nADS
IS
131
Interrupt
INTR0
O4
132
nRead
Strobe
nWrite
Strobe
RAM Data
Bus
nRD
IS
134
nWR
IS
Input. Used in asynchronous bus interfaces.
56-57, 60-
65, 46-48,
50-54, 35-
38, 40-42,
45, 25-28,
30-32, 34
RD[31:0]
I/O4 with
pullups
Bidirectional. Carries the local buffer memory
read and write data. Reads are always 32 bits
wide. Writes are controlled individually at the byte
level.
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