參數(shù)資料
型號(hào)： LAN91C95
英文描述： LAN Node Controller
中文描述： 網(wǎng)絡(luò)節(jié)點(diǎn)控制器
文件頁(yè)數(shù)： 20/55頁(yè)
文件大小： 482K
代理商： LAN91C95
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
SMSC DS – LAN91C110 REV. B
Page 20
Rev. 09/05/02
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be
received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.
BANK 0
OFFSET
NAME
6
COUNTER REGISTER
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared
when reading the register and do not wrap around beyond 15.
TYPE
SYMBOL
ECR
READ ONLY
HIGH
BYTE
NUMBER OF EXC. DEFFERED TX
NUMBER OF DEFFERED TX
0
0
0
0
0
0
0
0
LOW
BYTE
MULTIPLE COLLISION COUNT
SINGLE COLLISION COUNT
0
0
0
0
0
0
0
0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER bit
description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting
the rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted after one
collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions,
the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the NUMBER OF
DEFERRED TX field is incremented by one, even if the packet experienced multiple deferrals during its collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts
are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
BANK 0
OFFSET
NAME
8
MEMORY INFORMATION REGISTER
TYPE
SYMBOL
MIR
READ ONLY
HIGH
BYTE
FREE MEMORY AVAILABLE (IN BYTES * 256 * M)
1
1
1
1
1
1
1
1
LOW
BYTE
MEMORY SIZE (IN BYTES *256 * M)
1
1
1
1
1
1
1
1
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The
register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size.
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