參數(shù)資料
型號： LAN91C95
英文描述： LAN Node Controller
中文描述： 網(wǎng)絡(luò)節(jié)點控制器
文件頁數(shù)： 3/55頁
文件大?。?/td> 482K
代理商： LAN91C95
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
SMSC DS – LAN91C110 REV. B
Page 3
Rev. 09/05/02
TABLE OF CONTENTS
FEATURES................................................................................................................................1
GENERAL DESCRIPTION........................................................................................................1
FUNCTIONAL DESCRIPTION..................................................................................................9
DATA STRUCTURES AND REGISTERS...............................................................................13
T
YPICAL
F
LOW OF
E
VENTS FOR
T
RANSMIT
(A
UTO
R
ELEASE
= 0)..................................................36
T
YPICAL
F
LOW OF
E
VENTS FOR
T
RANSMIT
(A
UTO
R
ELEASE
= 1)..................................................37
T
YPICAL
F
LOW OF
E
VENTS FOR
R
ECEIVE
.....................................................................................38
OPERATIONAL DESCRIPTION .............................................................................................46
MAXIMUM GUARANTEED RATINGS*...................................................................................46
DC ELECTRICAL CHARACTERISTICS..................................................................................46
TIMING DIAGRAMS................................................................................................................49
LAN91C110 REV. B REVISIONS ..........................................................................................55
LIST OF TABLES
T
ABLE
1
- DESCRIPTION OF PIN FUNCTIONS........................................................................................................5
T
ABLE
2
- BUFFER TYPES..........................................................................................................................................7
T
ABLE
3
- I
NTERNAL
I/O S
PACE
M
APPING
.....................................................................................................................16
T
ABLE
4
- P
IN
P
ACKAGE
O
UTLINE
T
ABLE
....................................................................................................................54
LIST OF FIGURES
F
IGURE
1
- PIN CONFIGURATION.............................................................................................................................4
F
IGURE
2
- LAN91C110 BLOCK DIAGRAM..............................................................................................................8
F
IGURE
3
- LAN91C110 SYSTEM DIAGRAM............................................................................................................8
F
IGURE
4
-
LAN91C110 INTERNAL BLOCK DIAGRAM WITH DATAPATH......................................................12
F
IGURE
5
- DATA PACKET FORMAT......................................................................................................................13
F
IGURE
6
- INTERRUPT STRUCTURE.....................................................................................................................31
F
IGURE
7
- INTERRUPT SERVICE ROUTINE .........................................................................................................39
F
IGURE
8- RX INTR....................................................................................................................................................40
F
IGURE
9
- TX INTR....................................................................................................................................................41
F
IGURE
10
- TXEMPTY INTR (A
SSUMES AUTO RELEASE OPTION SELECTED
)............................................................42
F
IGURE
11
- DRIVE SEND AND ALLOCATE ROUTINES......................................................................................43
F
IGURE
12
- INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU....................................................45
F
IGURE
13
- ASYNCHRONOUS CYCLE -
N
ADS=0.................................................................................................49
F
IGURE
14
- ASYNCHRONOUS CYCLE
- USING
N
ADS........................................................................................49
F
IGURE
15
- ADDRESS LATCHING FOR ALL MODES..........................................................................................50
F
IGURE
16
- SRAM INTERFACE...............................................................................................................................51
F
IGURE
17
- MII I
NTERFACE
........................................................................................................................................53
F
IGURE
18
- 144 P
IN
TQFP P
ACKAGE
O
UTLINES
.........................................................................................................54
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