參數(shù)資料
型號(hào)： LAN91C94
廠商： SMSC Corporation
英文描述： ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM
中文描述： 的ISA / PCMCIA的單芯片以太網(wǎng)控制器與RAM
文件頁(yè)數(shù)： 18/55頁(yè)
文件大小： 482K
代理商： LAN91C94
SMSC DS – LAN91C110 REV. B
Page 18
Rev. 09/05/02
BANK 0
OFFSET
2
NAME
TYPE
SYMBOL
EPHSR
EPH STATUS REGISTER
READ ONLY
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet
completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use
the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used
for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.
HIGH
BYTE
TX
UNRN
LINK_
OK
Reserved
CTR
_ROL
EXC
_DEF
Reserved
LATCOL
Reserved
0
-nLNK
pin
0
0
0
0
0
0
LOW
BYTE
TX
DEFR
LTX
BRD
SQET
16COL
LTX
MULT
MUL
COL
SNGL
COL
TX_SUC
0
0
0
0
0
0
0
0
TXUNRN - Transmit Under Run. Set if under run occurs, it also clears TXENA bit in TCR. Cleared by setting TXENA high.
This bit may only be set if early TX is being used.
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value
of this bit generates an interrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by
reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte times. Cleared
at the end of every packet sent.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into
the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting
TXENA in TCR.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4
μ
s of the inter frame gap. Cleared at
the end of every packet sent.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit
frame.
SQET - Signal Quality Error Test. SQET bit is always set after first transmit, except if SWFDUP=1. As a consequence,
the STP_SQET bit in the TCR register cannot be set as it will always result in transmit fatal error. Transmission stops and
EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high.
16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.
Cleared when TXENA is set high.
LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit
frame.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LAN91C95TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
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