參數(shù)資料
型號(hào)： LAN91C110TQFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： FEAST FAST ETHERNET CONTROLLER FOR PCMCIA AND GENERIC 16-BIT APPLICATIONS
中文描述： 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 26/55頁(yè)
文件大?。?/td> 482K
代理商： LAN91C110TQFP
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
SMSC DS – LAN91C110 REV. B
Page 26
Rev. 09/05/02
Note 1:
Bits N2,N1,N0 bits are ignored by the LAN91C110 but should be used for command 0 to preserve software
compatibility with the LAN91C92 and future devices. They should be zero for all other commands.
Note 2:
When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
Note 3:
MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet
number has memory allocated to it.
COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed. Completion is
determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY
bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be
changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a
release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon
the trailing edge of command.
BANK 2
OFFSET
NAME
2
PACKET NUMBER REGISTER
TYPE
SYMBOL
PNR
READ/WRITE
Reserved
Reserved
PACKET NUMBER AT TX AREA
0
0
0
0
0
0
0
0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible
through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This
register is cleared by a RESET or a RESET MMU Command.
OFFSET
NAME
3
ALLOCATION RESULT REGISTER
This register is updated upon an ALLOCATE MEMORY MMU command.
TYPE
SYMBOL
ARR
READ ONLY
FAILED
Reserved
ALLOCATED PACKET NUMBER
1
0
0
0
0
0
0
0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the
pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT
in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:
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