參數(shù)資料
型號： LAN91C100FDTQFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： TQFP-208
文件頁數(shù)： 3/79頁
文件大?。?/td> 585K
代理商： LAN91C100FDTQFP
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 3
Rev.
10/14/2002
PRELIMINARY
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.1.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
Chapter 6
Chapter 7
7.1
7.2
7.3
7.4
Chapter 8
8.1
8.2
Chapter 9
Chapter 10
Chapter 11
General Description.............................................................................................................5
Pin Configuration.................................................................................................................6
Description of Pin Functions...............................................................................................7
Functional Description.......................................................................................................15
Description of Block...........................................................................................................................15
Clock Generator Block............................................................................................................................15
CSMA/CD BLOCK.............................................................................................................................15
DMA Block..............................................................................................................................................15
Arbiter Block ...........................................................................................................................................15
MMU Block .............................................................................................................................................16
BIU Block................................................................................................................................................16
MAC-PHY Interface Block ......................................................................................................................16
MII Management Interface Block............................................................................................................17
Serial EEPROM Interface.......................................................................................................................17
Data Structures and Registers ..........................................................................................19
Packet Format in Buffer Memory ......................................................................................................19
Typical Flow of Events for Transmit (Auto Release = 0)...................................................................41
Typical Flow of Events for Transmit (Auto Release = 1)...................................................................43
Typical Flow of Events for Receive...................................................................................................44
Memory Partitioning ..........................................................................................................................49
Interrupt Generation..........................................................................................................................50
Board Setup Information ..................................................................................................53
Application Considerations...............................................................................................56
Fast Ethernet Slave Adapter.............................................................................................................56
VL Local Bus 32 Bit Systems............................................................................................................56
High End ISA or Non-Burst EISA Machines......................................................................................59
EISA 32 Bit SLAVEEISA 32 Bit Slave...............................................................................................61
Operational Description ....................................................................................................64
Maximum Guaranteed Ratings*........................................................................................................64
DC Electrical Characteristics.............................................................................................................64
Timing Diagrams................................................................................................................67
Package Outlines.............................................................................................................77
LAN91C100FD REV. D Revisions ................................................................................79
LIST OF FIGURES
Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13
Figure 3.2 - LAN91C100FD System Diagram..............................................................................................................14
Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18
Figure 5.1 - Data Packet Format..................................................................................................................................19
Figure 5.2 - Interrupt Structure.....................................................................................................................................37
Figure 5.3 - Interrupt Service Routine..........................................................................................................................45
Figure 5.4 - RX INTR ...................................................................................................................................................46
Figure 5.5 - TX INTR....................................................................................................................................................47
Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected)......................................................................48
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