參數(shù)資料
型號(hào)： LAN91C100FDTQFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： TQFP-208
文件頁(yè)數(shù)： 27/79頁(yè)
文件大?。?/td> 585K
代理商： LAN91C100FDTQFP
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 27
Rev.
10/14/2002
PRELIMINARY
These register default to FFh, which should be interpreted as 256.
BANK 0
OFFSET
A
NAME
MEMORY
CONFIGURATION
REGISTER
TYPE
SYMBOL
MCR
Lower Byte - READ/WRITE
Upper Byte - READ ONLY
HIGH
BYTE
LOW
BYTE
MEMORY SIZE MULTIPLIER
0
0
1
1
0
1
0
1
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
0
0
0
0
0
0
0
0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve
memory to be used later for transmit, limiting the amount of memory that receive packets can use. When
programmed for zero, the memory allocation between transmit and receive is completely dynamic. When
programmed for a non-zero value, the allocation is dynamic if the free memory exceeds the programmed
value, while receive allocation requests are denied if the free memory is less or equal to the programmed
value. This register defaults to zero upon reset. It is not affected by the RESET MMU command.
The value written to the MCR is a reserved memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for transmit plus the reserved space for transmit is required
to be constant (rather than grow with transmit allocations) the CPU should update the value of this register
after allocating or releasing memory.
The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where
M is the Memory Size Multiplier. M=2 for the LAN91C100FD. A value of 04h in the lower byte of the MCR
is equal to one 2K page (4 * 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0
and 1 of the MCR should be written to 1 only when the entire memory is being reserved for transmit (i.e.,
low byte of MCR = FFh).
BANK1
OFFSET
0
NAME
TYPE
SYMBOL
CR
CONFIGURATION REGISTER
READ/WRITE
The Configuration Register holds bits that define the adapter configuration and are not expected to change
during run-time. This register is part of the EEPROM saved setup.
HIGH
BYTE
LOW
BYTE
MII
SELECT
1
1
NO
WAIT
0
Reserved
FULL
STEP
0
INT
SEL1
0
0
AUI
SELECT
0
0
0
1
0
0
INT
SEL0
0
1
0
1
1
0
1
MII SELECT - Used to select the network interface port. When set, the LAN91C100FD will use its MII port
and interface a PHY device at the nibble rate. When clear, the LAN91C100FD will use its 10 Mbps ENDEC
interface. This bit drives the MII SEL pin. Switching between ports should be done with transmitter and
receiver disabled and no transmit/receive packets in progress.
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相關(guān)代理商/技術(shù)參數(shù)
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LAN91C100QFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
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