參數(shù)資料
型號(hào)： LAN91C100-FD-SS
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： FEAST Fast Ethernet Controller with Full Duplex Capability
中文描述： 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： GREEN, QFP-208
文件頁(yè)數(shù)： 48/67頁(yè)
文件大?。?/td> 369K
代理商： LAN91C100-FD-SS
SMSC DS – LAN91C100FD REV. B
Page 48
Rev. 01-20-06
APPLICATION CONSIDERATIONS
The LAN91C100FD is envisioned to fit a few different bus types. This section describes the basic guidelines, system level
implications and sample configurations for the most relevant bus types. All applications are based on buffered
architectures with a private SRAM bus.
FAST ETHERNET SLAVE ADAPTER
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
a) LAN91C100FD chip
b) Four SRAMs (32k x 8 - 25ns)
c)
Serial EEPROM (93C46)
d) Mbps ENDEC and transceiver chip
e) Mbps MII compliant PHY
f)
Some bus specific glue logic
Target systems:
a) VL Local Bus 32 bit systems
b) High-end ISA or non-burst EISA machines
c)
EISA 32 bit slave
VL Local Bus 32 Bit SystemsVL Local Bus 32 bit systemsVL Local Bus 32 bit systems
On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed as a 32 bit peripheral in terms of the
bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the
DATA REGISTER could use byte, word, or dword instructions.
Table 3 - VL Local Bus Signal Connections
VL BUS
SIGNAL
LAN91C100
SIGNAL
NOTES
A2-A15
A2-A15
Address bus used for I/O space and register decoding, latched by
nADS rising edge, and transparent on nADS low time.
M/nIO
AEN
Qualifies valid I/O decoding - enabled access when low. This signal
is latched by nADS rising edge and transparent on nADS low time.
W/nR
W/nR
Direction of access. Sampled by the LAN91C100FD on first rising
clock that has nCYCLE active. High on writes, low on reads.
nRDYRTN
nRDYRTN
Ready return. Direct connection to VL bus.
nLRDY
nSRDY and some
logic
nSRDY has the appropriate functionality and timing to create the VL
nLRDY except that nLRDY behaves like an open drain output most
of the time.
LCLK
LCLK
Local Bus Clock. Rising edges used for synchronous bus interface
transactions.
nRESET
RESET
Connected via inverter to the LAN91C100FD.
nBE0 nBE1
nBE2 nBE3
nBE0 nBE1
nBE2 nBE3
Byte enables. Latched transparently by nADS rising edge.
nADS
nADS, nCYCLE
Address Strobe is connected directly to the VL bus. nCYCLE is
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LAN91C100-FD-ST 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST Fast Ethernet Controller with Full Duplex Capability
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LAN91C100QFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
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