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參數(shù)資料
| 型號： | LAN91C100-FD-SS |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FEAST Fast Ethernet Controller with Full Duplex Capability |
| 中文描述： | 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | GREEN, QFP-208 |
| 文件頁數(shù)： | 19/67頁 |
| 文件大?。?/td> | 369K |
| 代理商： | LAN91C100-FD-SS |
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SMSC DS – LAN91C100FD REV. B
Page 19
Rev. 01-20-06
BANK SELECT REGISTER
OFFSET
E
NAME
TYPE
SYMBOL
BSR
BANK SELECT
REGISTER
READ/WRITE
HIGH
BYTE
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LOW
BYTE
BS2
BS1
BS0
X
X
X
X
X
0
0
0
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the
register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C100FD.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.
Note that the bank select register can be accessed as a doubleword at offset Ch, as a word at offset Eh, or as at
offset Fh, however a doubleword write to offset Ch will write the BANK SELECT REGISTER but will not write the
registers Ch and Dh.
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where BANK7 is
selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers.
Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done
if the Revision Control register indicates the device is the LAN91C100FD.
BANK 0
OFFSET
NAME
0
TRANSMIT CONTROL
REGISTER
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
LOOP
SQET
0
0
0
0
LOW
BYTE
0
0
0
0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from recognizing carrier
sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision related status bits in the EPHSR are
not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and SNGL COL). Uses COL100 as flow control, limiting
backoff and jam to 1 clock each before inter-frame gap, then retry will occur after IFG. If COL100 is active during
preamble, full preamble will be output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no
effect. This bit should be low for non-MII operation.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults low. When
EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h, TXEN100 = TXEN = 0, TXD = 1.
The following and external inputs are blocked: CRS=CRS100=0, COL=COL100=0, RX_DV= RX_ER=0.
TYPE
SYMBOL
TCR
READ/WRITE
SWFDUP
0
EPH
STP
FDUPLX
MON_
CSN
0
0
NOCRC
0
0
0
PAD_EN
0
0
0
0
FORCOL
LOOP
TXENA
0
0
0
0
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| LAN91C100-FD | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
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| LAN91C100FDREVD | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN91C100FD-SS | 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C100-FD-ST | 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST Fast Ethernet Controller with Full Duplex Capability |
| LAN91C100FD-ST | 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C100FDTQFP | 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C100QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
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