參數(shù)資料
型號(hào): LAN9117
廠商: SMSC Corporation
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 高性能單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 48/131頁
文件大?。?/td> 1531K
代理商: LAN9117
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
48
SMSC LAN9117
DATASHEET
3.13.1
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9117 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The following diagram illustrates the buffer format.
Figure 3.14, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9117. It should be
noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must
be taken into account when calculating the actual TX data FIFO usage. Please refer to
Section 3.13.5,
"Calculating Actual TX Data FIFO Usage," on page 52
for a detailed explanation on calculating the
actual TX data FIFO usage.
Note 3.14
The LAN9117 host bus interface supports 16-bit bus transfers; internally, all data paths are
32-bits wide.
Figure 3.14
describes the host write ordering for pairs of atomic 16-bit
transactions.
3.13.2
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
Figure 3.14 TX Buffer Format
TX Command 'A'
Offset + Data DWORD0
.
.
.
.
.
Last Data & PAD
0
31
1st
2nd
3rd
Last
Host Write
Order
Optional Pad DWORD0
.
.
.
Optional Pad DWORDn
TX Command 'B'
Optional offset DWORD0
.
.
.
Optional offset DWORDn
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