參數(shù)資料
型號: LAN9117
廠商: SMSC Corporation
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 高性能單芯片10/100非PCI以太網(wǎng)控制器
文件頁數(shù): 121/131頁
文件大?。?/td> 1531K
代理商: LAN9117
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
121
Revision 1.1 (05-17-05)
DATASHEET
Note:
The “Data Bus” width is 16 bits
Note:
An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9117 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
csh
nCS, nRD Deassertion Time
13
ns
t
csdv
nCS, nRD Valid to Data Valid
30
ns
t
acyc
Address Cycle Time
45
t
asu
Address, FIFO_SEL Setup to nCS, nRD Valid
0
ns
t
adv
Address Stable to Data Valid
40
t
ah
Address, FIFO_SEL Hold Time
0
ns
t
don
Data Buffer Turn On Time
0
ns
t
doff
Data Buffer Turn Off Time
7
ns
t
doh
Data Output Hold Time
0
ns
Data Bus
nCS, nRD
FIFO_SEL
A[2:1]
相關(guān)PDF資料
PDF描述
LAN9117-MD HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9117-MT HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9118 HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MD HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MT HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
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