參數(shù)資料
型號: LAN9117-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 97/131頁
文件大?。?/td> 1531K
代理商: LAN9117-MT
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9117
97
Revision 1.1 (05-17-05)
DATASHEET
5.4.1
MAC_CR—MAC Control Register
This register establishes the RX and TX operation modes and controls for address filtering and packet
filtering.
Table 5.6 LAN9117 MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
INDEX
SYMBOL
REGISTER NAME
DEFAULT
1
MAC_CR
MAC Control Register
00040000h
2
ADDRH
MAC Address High
0000FFFFh
3
ADDRL
MAC Address Low
FFFFFFFFh
4
HASHH
Multicast Hash Table High
00000000h
5
HASHL
Multicast Hash Table Low
00000000h
6
MII_ACC
MII Access
00000000h
7
MII_DATA
MII Data
00000000h
8
FLOW
Flow Control
00000000h
9
VLAN1
VLAN1 Tag
00000000h
A
VLAN2
VLAN2 Tag
00000000h
B
WUFF
Wake-up Frame Filter
00000000h
C
WUCSR
Wake-up Control and Status
00000000h
Offset:
1
Attribute:
R/W
Default Value:
00040000h
Size:
32 bits
BITS
DESCRIPTION
31
Receive All Mode (RXALL).
When set, all incoming packets will be received and passed on to the
address filtering Function for processing of the selected filtering mode on the received frame. Address
filtering then occurs and is reported in Receive Status. When reset, only frames that pass Destination
Address filtering will be sent to the Application.
30-24
Reserved
23
Disable Receive Own (RCVOWN).
When set, the MAC disables the reception of frames when TXEN
is asserted. The MAC blocks the transmitted frame on the receive path. When reset, the MAC receives
all packets the PHY gives, including those transmitted by the MAC.This bit should be reset when the
Full Duplex Mode bit is set.
22
Reserved
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