參數(shù)資料
型號(hào): LAN9117-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù): 71/131頁(yè)
文件大?。?/td> 1531K
代理商: LAN9117-MT
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)當(dāng)前第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.1
SMSC LAN9117
71
Revision 1.1 (05-17-05)
DATASHEET
Register Nomenclature and Access Attributes
5.2
RX and TX FIFO Ports
The LAN9117 contains four host-accessible FIFOs: the RX Status, RX data, TX Status, and TX data
FIFOs. The sizes of the RX and TX data FIFOs, as well as the RX Status FIFO are configurable
through the CSRs.
5.2.1
RX FIFO Ports
The RX data Path consists of two Read-Only FIFOs; the RX Status and data. The RX Status FIFO can
be read from two locations. The RX Status FIFO Port will perform a destructive read, thus “Popping”
the data from the RX Status FIFO. There is also the RX Status FIFO PEEK location. This location
allows a non-destructive read of the top (oldest) location of the FIFO.
The RX data FIFO only allows destructive reads. It is aliased in 8 DWORD locations (accessed from
the bus interface as 8 pairs of atomic 16-bit accesses). The host may access any of the locations since
they all contain the same data and perform the same function.
5.2.2
TX FIFO Ports
The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read
from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data
from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a non-
destructive read of the top (oldest) location of the FIFO.
SYMBOL
DESCRIPTION
RO
Read Only:
If a register is read only, writes to this register have no effect.
WO
Write Only:
If a register is write only, reads always return 0.
R/W
Read/Write:
A register with this attribute can be read and written
R/WC
Read/Write Clear:
A register bit with this attribute can be read and written. However, a write
of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
RC
Read to Clear:
A register bit with this attribute is cleared when read.
LL
Latch Low:
Clear on read of register
LH
Latch High:
Clear on read of register
SC
Self-Clearing
NASR
Not Affected by Software Reset
Reserved
Bits
Unless otherwise stated, reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
Reserved
Registers
In addition to reserved bits within a register, the LAN9117 contains address locations in the
configuration space that are marked “Reserved. When a “Reserved” register location is read,
a random value can be returned. Registers that are marked as “Reserved” must not be
modified by system software. Writes to “Reserved” registers may cause system failure.
Default
Value Upon
Reset
Upon a Reset (System reset, Software Reset, or POR), the LAN9117 sets its internal
configuration registers to predetermined
default
states. The default state represents the
minimum functionality feature set required to successfully bring up the system. Hence, it does
not represent the optimal system configuration. It is the responsibility of the system
initialization software to properly determine the operating parameters and optional system
features that are applicable, and to program the LAN9117 registers accordingly.
相關(guān)PDF資料
PDF描述
LAN9118 HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MD HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN9118-MT HIGH PERFORMANCE SINGLE CHIP 10/100NON PCI ETHERNET CONTROLLER
LAN91C100-FD-SS FEAST Fast Ethernet Controller with Full Duplex Capability
LAN91C100-FD FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAN9118 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_05 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118_07 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
LAN9118-MD 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN9118-MT 功能描述:以太網(wǎng) IC Ethernet IC 32bit High Performance RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray