參數(shù)資料
型號(hào)： L6740LTR
廠商： 意法半導(dǎo)體
英文描述： Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述： 混合控制器（4 1對(duì)AMD SVID和PVID）處理器
文件頁(yè)數(shù)： 38/44頁(yè)
文件大?。?/td> 657K
代理商： L6740LTR
System control loop compensation
L6740L
38/44
Figure 17.
Control loop bode diagram and fine tuning (not in scale).
To obtain the desired shape an R
F
-C
F
series network is considered for the Z
F
(s)
implementation. A zero at
ω
F
=1/R
F
C
F
is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero
ω
F
in correspondence with the L-
C resonance assures a simple -20dB/Dec. shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing
ω
F
=
ω
LC
and imposing the cross-
over frequency
ω
T
as desired obtaining (always considering that
ω
T
might be not higher than
1/10th of the switching frequency F
SW
):
9.1
Compensation network guidelines
The Compensation Network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See
Figure 17
):
–
Increase R
F
to increase the system bandwidth accordingly;
–
Decrease R
F
to decrease the system bandwidth accordingly;
–
Increase C
F
to move
ω
F
to low frequencies increasing as a consequence the
system phase margin.
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (d
MAX
) or minimum (0) value. The output voltage
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by V
OUT
(while it is charged by d
MAX
V
IN
-V
OUT
during a load
appliance).
dB
ω
Z
F
(s)
G
LOOP
(s)
K
ω
LC
=
ω
F
ω
ESR
ω
T
R
F
[dB]
dB
ω
Z
F
(s)
G
LOOP
(s)
K
ω
LC
=
ω
F
ω
ESR
ω
T
R
F
[dB]
R
F
C
F
R
F
R
V
V
IN
---------------------------------
10
------
ω
T
N
R
LL
ESR
+
)
------------------------------------------
=
C
F
C
L
R
F
-------------------
=
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