參數(shù)資料
型號(hào): L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對(duì)AMD SVID和PVID)處理器
文件頁數(shù): 10/44頁
文件大?。?/td> 657K
代理商: L6740LTR
Pins description and connection diagrams
L6740L
10/44
19
C
CS4+
Channel 4 Current Sense Positive Input. Connect through an R-C filter
to the phase-side of the channel 4 inductor. When working at 2 or 3
phase, directly connect to V
out_CORE
.
See
Section 9
for proper layout of this connection.
20
CS4-
Channel 4 Current Sense Negative Input. Connect through a R
G
resis-
tor to the output-side of the channel inductor. When working at 2 or 3
phase, connect through R
G
to CS4+.
See
Section 9
for proper layout of this connection.
21
OC_PHASE
Per-Phase Over Current (CORE Section).
Internally set to 1.24V, connecting to SGND with a resistor R
OC_TH
it
programs the OC threshold per-phase. See
Section 7.4.1
for details.
22
NC
Not internally connected.
23
N
S
NB_ISEN
NB Current Sense Pin.
Used for NB voltage positioning and NB_OCP. Connect through a resis-
tor R
ISEN
to the relative LS Drain. See
Section 7.4
for details.
24
NC
Not internally connected.
25,
26
P
I
VID4, VID5
Voltage IDentification Pins.
Internally pulled-low by 10
μ
A, they are used to program the output
voltage. Used only in PVI-Mode, ignored when in SVI-Mode.See
Section 5
for details.
27
OSC / FLT
OSC
: It allows programming the switching frequency F
SW
of both Sec-
tions. Switching frequency can be increased according to the resistor
R
OSC
connected from the pin to. SGND with a gain of 6.8kHz/μA (see
Section 8
for details). If floating, the switching frequency is 150kHz per
phase.
FLT
: The pin is forced high (3.3V) in case of an OV / UV fault. To
recover from this condition, cycle VCC or the EN pin. See
Section 7
for
details.
28
C
OC_AVG /
LI
Average Over Current and Load Indicator Pin.
A current proportional to the current delivered by the CORE Section (a
copy of the DROOP current) is sourced through this pin.
The Average-OC threshold is programmed by connecting a resistor
R
OC_AVG
to SGND. When the generated voltage crosses the OC_AVG
threshold (V
OC_AVGTH
= 2.5V Typ) the device latches with all mosfets
OFF (to recover, cycle VCC or the EN pin).
A load indicator with 2.5V end-of-scale is then implemented.
See
Section 7.4.1
for details.
29
N
NB_OS
Offset Programming Pin.
Internally set to 1.24V, connecting a R
OS_NB
resistor to SGND allows
setting a current that is mirrored into NB_FB pin in order to program a
positive offset according to the selected R
FB_NB
. Short to SGND to dis-
able the function. See
Section 6.7
for details.
30
NB_FBG
Remote Ground Sense.
Connect to the negative side of the load to perform remote sense. See
Section 9
for proper layout of this connection.
Table 2.
Pin description (continued)
Pin#
Name
Function
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