參數(shù)資料
型號: L6740LTR
廠商: 意法半導(dǎo)體
英文描述: Hybrid controller (4+1) for AMD SVID and PVID processors
中文描述: 混合控制器(4 1對AMD SVID和PVID)處理器
文件頁數(shù): 28/44頁
文件大?。?/td> 657K
代理商: L6740LTR
Output voltage positioning
L6740L
28/44
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to SGND.
Note:
In the above formulas, R
FB_NB
has to be considered being the total resistance connected
between NB_FB pin and the regulated voltage.
6.8
NB section - Maximum Duty-Cycle limitation
To provide proper time for current-reading across the Low-Side MOSFET, the device imple-
ments a duty-cycle limitation for the NB Section. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
6.9
On-The-Fly VID transitions
L6740L manages On-The-Fly VID Transitions that allow the Output Voltage of both sections
to modify during normal device operation for CPU power management purposes. OV, UV
and PWRGOOD signals are masked during every OTF-VID Transition and they are re-acti-
vated with a 16 clock cycle delay to prevent from false triggering.
When changing dynamically the regulated voltage (OTF-VID), the system needs to charge
or discharge the output capacitor accordingly. This means that an extra-current I
OTF-VID
needs to be delivered (especially when increasing the output regulated voltage) and it must
be considered when setting the over current threshold of both the sections. This current
results:
where dV
OUT
/ dT
VID
depends on the operative mode (3mV/
μ
sec. in SVI or externally driven
in PVI).
Overcoming the OC threshold during the dynamic VID causes the device latch and disable.
Dynamic VID transition is managed in different ways according to the device operative
mode:
PVI mode.
L6740L checks for VID code modifications (See
Figure 11
) on the rising-edge of an
internal additional OTFVID-clock and waits for a confirmation on the following falling
edge. Once the new code is stable, on the next rising edge, the reference starts
stepping up or down in LSB increments every two OTFVID-clock cycle until the new
VID code is reached. During the transition, VID code changes are ignored; the device
R
OS_NB
V
OS_NB
-------------------
R
FB_NB
=
T
ON_NB(max)
0.80 T
SW
0.40 T
SW
I
NB_ISEN
I
NB_ISEN
0
μ
A
=
35
μ
A
=
=
I
OTF-VID
C
OUT
dV
dT
VID
-----------------
=
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