參數(shù)資料
型號(hào)： L64250JC15
廠商： Innovasic Semiconductor
英文描述： Histogram/Hough Transform Processor
中文描述： 直方圖/ Hough變換處理器
文件頁(yè)數(shù)： 13/21頁(yè)
文件大?。?/td> 100K
代理商： L64250JC15
IA64250
Histogram/Hough Transform Processor
Marker Circuitry:
When ACC RAM is accessed, the marker circuitry in the marker memory is updated. The
user can specify up to seven values of grey level and the associated count will be stored in
the mode memory. Setting func = 1 in the control memory register will accomplish this. By
setting func = 0, the user can specify a particular count and the marker memory will be
updated with the last grey value whose count is equal to (or just exceeds) the count of
interest.
The maximum count, and the grey value which it occurred at, are also updated during each
I/O cycle and stored in mode memory locations 0-3.
If the accumulated histogram is being computed, i.e. the EQ bit in the mode register is set,
then the maximum count register will be equal to the number of pixels scanned, and the grey
value will be the maximum grey level occurring in the image.
Reading and Writing the LUT:
Data input to and output from the LUT RAM is also controlled by CLK2 and STARTIOn.
On the falling edge of STARTIOn, the I/O cycle is initiated with the LUT RAM addresses
being read or written sequentially with each cycle of CLK2. This process is controlled by the
address counter in the controller block.
LUT read/write operations are defined by the io0-1 bits in the control memory. Code 10 is
used to read the LUT RAM. Data will be read sequentially and output on the DO bus. To
write the LUT RAM, code 11 is used in the control memory. Input from the CI bus is
stored in successive addresses with each cycle of CLK2.
The LUT RAM can also be addressed from the DI bus. A typical application would be
histogram equalization. The LUT would contain the equalized transfer function generated
by transferring ACC RAM data to the LUT with EQ high. Setting the FN0-FN1 bits for
histogram computation configures data from the DI bus to address both the ACC RAM and
the LUT. Equalized data is then output on the VDO bus. Histogram computation is taking
place concurrently. In this case CLK2 should be connected to CLK1 to achieve an
equalization rate equal to the pixel rate.
I/O SEQUENCES:
Read ACC, Read LUT, Transfer ACC to LUT
I/O operations can be divided into two groups: those that end before all 512 elements of
the ACC or LUT RAM have been accessed (short cycle) and those that end after all 512
elements have been accessed (long cycle). All I/O cycles are initiated by a high to low
transition on the STARTIOn input signal. AT must be low in each case.
The short cycle is terminated when STARTIOn is returned high before all elements of the
RAM have been read. The first data value appears on the DO pins three CLK2 cycles after
STARTIOn goes low. The IODV flag also goes high after three cycles, indicating that the
Data Sheet
As of Production Ver. 01
Copyright
2000
innov
ASIC
The End of Obsolescence
ENG211001219-01
www.innovasic.com
Customer Support:
Page 13 of 21
1-888-824-4184
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