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參數(shù)資料
| 型號： | L64250JC15 |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | Histogram/Hough Transform Processor |
| 中文描述： | 直方圖/ Hough變換處理器 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 100K |
| 代理商： | L64250JC15 |
IA64250
Histogram/Hough Transform Processor
LUT RAM Hough Transform Mode
(45 <
f
￡
90):
Address
Memory Contents
0
0*cot
φ
1
1*cot
φ
.
.
.
.
.
511
511*cot
φ
LUT RAM Find Pixel Mode:
Memory Contents
Address
0-5
0
Flag for Grey Value
0
1
Flag for Grey Value
1
.
.
.
.
.
511
Flag for Grey Value
511
COMPUTATION MODE:
Histogram Computation:
During histogram computation, the ACC RAM and LUT RAM form the active elements of
the data path. The ACC RAM is addressed by the controller block. The ACC RAM address
is the DI input signal. The data addressed by the DI signal is incremented if the DV input
signal is high, otherwise the data is left unchanged. The LUT is not used in the computation
of the histogram and can concurrently modify the image by a user-defined transfer function.
The DI signal addresses the LUT and the LUT data appears on the VDO output pins two
clock cycles later.
Histogram equalization can be performed in real time. The histogram is stored in the ACC
RAM. The equalization transfer function must be computed and transferred into the LUT
RAM. Then during the next frame as a new histogram is being computed, data will also be
equalized in real time and passed to the VDO output pins.
Data Sheet
As of Production Ver. 01
Copyright
2000
innov
ASIC
The End of Obsolescence
ENG211001219-01
www.innovasic.com
Customer Support:
Page 10 of 21
1-888-824-4184
.
.
.
6-7
t0
8
Not Used
t1
.
.
.
Tag
Bit
t511
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