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參數(shù)資料
| 型號： | KSZ8895MQI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 99/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 5PORT 128PQFP |
| 特色產(chǎn)品： | KSZ8895MQ Ethernet Switches |
| 標準包裝： | 66 |
| 系列： | * |
| 其它名稱： | 576-3997 |
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PIC16(L)F1782/3
DS41579C-page 80
Preliminary
2011-2012 Microchip Technology Inc.
8.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
GIE bit of the INTCON register
Interrupt Enable bit(s) for the specific interrupt
event(s)
PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 or PIE2 registers)
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
Critical registers are automatically saved to the
shadow registers (See “Section 8.5 “Automatic
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
8.2
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 8-2
and Figure 8.3 for more details.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KSZ8895MQXCA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關 接口:I2C，SPI 標準:10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:0°C ~ 70°C 封裝/外殼:128-BFQFP 供應商器件封裝:128-PQFP（14x20） 標準包裝:66 |
| KSZ8895MQXIA | 功能描述:Ethernet Switch 10/100 Base-T/TX I2C, SPI Interface 128-PQFP (14x20) 制造商:microchip technology 系列:- 包裝:托盤 零件狀態(tài):有效 協(xié)議:以太網(wǎng) 功能:開關 接口:I2C，SPI 標準:10/100 Base-T/TX 電壓 - 電源:1.8V，2.5V，3.3V 電流 - 電源:129mA 工作溫度:-40°C ~ 85°C 封裝/外殼:128-BFQFP 供應商器件封裝:128-PQFP（14x20） 標準包裝:66 |
| KSZ8895RQ | 功能描述:以太網(wǎng) IC 5-port Switch, one SW5-RMII and one P5-RMII Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895RQ TR | 功能描述:以太網(wǎng) IC 5-port Switch, one SW5-RMII and one P5-RMII Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8895RQ-EVAL | 功能描述:以太網(wǎng)開發(fā)工具 5-port Switch, one SW5-RMII and one P5-RMII Interface - Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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