參數(shù)資料
型號: KSZ8895MQI
廠商: Micrel Inc
文件頁數(shù): 42/119頁
文件大小: 0K
描述: IC ETHERNET SWITCH 5PORT 128PQFP
特色產(chǎn)品: KSZ8895MQ Ethernet Switches
標準包裝: 66
系列: *
其它名稱: 576-3997
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 29
PIC16(L)F1782/3
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 0
00Ch PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
00Dh PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
00Eh PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
00Fh —
Unimplemented
010h PORTE
—RE3
---- x--- ---- u---
011h PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
012h PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
C3IF
CCP2IF
0000 0-00 0000 0-00
013h —
Unimplemented
014h PIR4
PSMC2TIF
PSMC1TIF
PSMC2SIF
PSMC1SIF --00 --00 --00 --00
015h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
016h TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
018h T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—TMR1ON
0000 00-0 uuuu uu-u
019h T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00 uuuu uxuu
016h TMR2
Holding Register for the Least Significant Byte of the 16-bit TMR2 Register
xxxx xxxx uuuu uuuu
017h PR2
Holding Register for the Most Significant Byte of the 16-bit TMR2 Register
xxxx xxxx uuuu uuuu
018h T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
01Dh
to
01Fh
Unimplemented
Bank 1
08Ch TRISA
PORTA Data Direction Register
1111 1111 1111 1111
08Dh TRISB
PORTB Data Direction Register
1111 1111 1111 1111
08Eh TRISC
PORTC Data Direction Register
1111 1111 1111 1111
08Fh —
Unimplemented
090h TRISE
(2)
---- 1--- ---- 1---
091h PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
092h PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
C3IE
CCP2IE
0000 0-00 0000 0-00
093h —
Unimplemented
094h PIE4
PSMC2TIE
PSMC1TIE
PSMC2SIE
PSMC2SIE --00 --00 --00 --00
095h OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
096h PCON
STKOVF
STKUNF
—RWDT
RMCLR
RI
POR
BOR
00-1 11qq qq-q qquu
097h WDTCON
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
--01 0110 --01 0110
098h OSCTUNE
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000 --00 0000
099h OSCCON
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
SCS1
SCS0
0011 1-00 0011 1-00
09Ah OSCSTAT
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
00q0 --00 qqqq --0q
09Bh ADRESL
A/D Result Register Low
xxxx xxxx uuuu uuuu
09Ch ADRESH
A/D Result Register High
xxxx xxxx uuuu uuuu
09Dh ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
-000 0000 -000 0000
09Eh ADCON1
ADFM
ADCS2
ADCS1
ADCS0
ADNREF
ADPREF1
ADPREF0
0000 -000 0000 -000
09Fh ADCON2
TRIGSEL3
TRIGSEL2
TRIGSEL1
TRIGSEL0
CHSN3
CHSN2
CHSN1
CHSN0
000- -000 000- -000
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
These registers can be addressed from any bank.
2:
Unimplemented, read as ‘1’.
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