參數(shù)資料
型號: KSZ8873MLLJ
廠商: Micrel Inc
文件頁數(shù): 106/108頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標準包裝: 160
系列: *
其它名稱: 576-3996
2008 Microchip Technology Inc.
DS39631E-page 95
PIC18F2420/2520/4420/4520
REGISTER 9-3:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1
U-0
R/W-0
U-0
R/W-0
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INT2IP:
INT2 External Interrupt Priority bit
1
=High priority
0
= Low priority
bit 6
INT1IP:
INT1 External Interrupt Priority bit
1
=High priority
0
= Low priority
bit 5
Unimplemented:
Read as ‘0’
bit 4
INT2IE:
INT2 External Interrupt Enable bit
1
= Enables the INT2 external interrupt
0
= Disables the INT2 external interrupt
bit 3
INT1IE:
INT1 External Interrupt Enable bit
1
= Enables the INT1 external interrupt
0
= Disables the INT1 external interrupt
bit 2
Unimplemented:
Read as ‘0’
bit 1
INT2IF:
INT2 External Interrupt Flag bit
1
= The INT2 external interrupt occurred (must be cleared in software)
0
= The INT2 external interrupt did not occur
bit 0
INT1IF:
INT1 External Interrupt Flag bit
1
= The INT1 external interrupt occurred (must be cleared in software)
0
= The INT1 external interrupt did not occur
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
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