參數(shù)資料
型號(hào): KSZ8873MLLJ
廠商: Micrel Inc
文件頁(yè)數(shù): 105/108頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
系列: *
其它名稱: 576-3996
PIC18F2420/2520/4420/4520
DS39631E-page 94
2008 Microchip Technology Inc.
REGISTER 9-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
—TMR0IP
—RBIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RBPU:
PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0:
External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 5
INTEDG1:
External Interrupt 1 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 4
INTEDG2:
External Interrupt 2 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 3
Unimplemented:
Read as ‘0’
bit 2
TMR0IP:
TMR0 Overflow Interrupt Priority bit
1
=High priority
0
= Low priority
bit 1
Unimplemented:
Read as ‘0’
bit 0
RBIP:
RB Port Change Interrupt Priority bit
1
=High priority
0
= Low priority
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature allows for software polling.
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