參數(shù)資料
型號: KSZ8864RMN
廠商: Micrel Inc
文件頁數(shù): 72/111頁
文件大小: 0K
描述: IC ETHERNET SW 4PORT 64QFN
標(biāo)準(zhǔn)包裝: 348
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: MII,RMII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(8x8)
包裝: 托盤
配用: 576-3869-ND - BOARD EVALUATION FOR KSZ8864RMN
其它名稱: 576-3787
KSZ8864RMN-ND
1997 Microchip Technology Inc.
DS30444E - page 63
PIC16C9XX
11.0
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
Refer to Application Note AN578,
"Use of the SSP
Module in the I 2C Multi-Master Environment."
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
bit 6:
CKE: SPI Clock Edge Select (Figure 11-5, Figure 11-6, and Figure 11-7)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit was
detected last)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit was
detected last)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
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