參數(shù)資料
型號: KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 61/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標準包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
46
M9999-100207-1.5
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C)
This register is written by the CPU when there are frame data in receive buffer to be processed.
The following table shows the register bit fields.
Bit
Default \
R/W
Description
31 – 0
0x00000000
WO
WRSC Receive Start Command
When written with any value, the Receive DMA checks for descriptors to
be acquired. If no descriptor is available, the receive process returns to
suspended state and waits for the next receive restart command. If
descriptiors are available, the receive process resumes.
This bit is self-clearing.
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)
This register is used for the Transmit Descriptor List Base Address. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8842-PMQL/PMBL behavior is unpredictable when
the lists are not word-aligned.
The following table shows the register bit fields.
Bit
Default
R/W
Description
31 – 0
0x0
RW
WSTL Start of Transmit List
Note: Write can only occur when the transmit process stopped.
Receive Descriptor List Base Address Register (RDLB Offset 0x0014)
This register is used for the Receive descriptor list base address. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8842-PMQL/PMBL behavior is unpredictable when
the lists are not word-aligned.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 – 0
0x0
RW
WSRL Start of Receive List
Note: Write can only occur when the transmit process stopped.
Reserved (Offset 0x0018)
The following table shows the register bit fields.
Bit
Default
R/W
Description
31 – 0
0x0
RO
Reserved
Reserved (Offset 0x001C)
The following table shows the register bit fields.
Bit
Default
R/W
Description
31 – 0
0x0
RO
Reserved
MAC Multicast Table 0 Register (MTR0 Offset 0x0020)
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of
the CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within
the register.
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