參數資料
型號: KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁數: 56/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標準包裝: 1
主要目的: 接口,以太網控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產品目錄頁面: 1114 (CN2011-ZH PDF)
相關產品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
41
M9999-100207-1.5
Bit
Type
Default
Description
2
Command
0
Master Operation
When set, the KSZ8842-PMQL/PMBL is capable of acting as a bus
master.
When reset, the KSZ8842-PMQL/PMBL capability to generate PCI
accesses is disabled.
For normal operation, this bit must be set.
1
Command
0
Memory Space Access
When set, the KSZ8842-PMQL/PMBL responds to memory space
accesses.
When reset, the KSZ8842-PMQL/PMBL does not respond to
memory space accesses.
0
Reserved
0
Reserved
Configuration Revision Register (CFRV Offset 08H)
The CFRV register contains the KSZ8842-PMQL/PMBL revision number. The following table shows the CFRV register
bit fields.
Bit
Default
Description
31 – 24
0x02
Base Class
Indicates the network controller, and is equal to 2H.
23 – 16
0x00
Subclass
Indicates the Fast/Gigabit Ethernet chip, and is equal to 00H.
15 – 8
0x00
Reserved
7 – 4
0x1
Revision Number
Indicates the KSZ8842-PMQL/PMBL revision number, and is equal to 1H.
This number is incremented for subsequent revision.
3 – 0
0x0
Step Number
Indicates the KSZ8842-PMQL/PMBL step number, and is equal to 0H (chip
revision A). This number is incremented for subsequent KSZ8842-
PMQL/PMBL steps within the current revision.
Configuration Latency Timer Register (CFLT Offset 0CH)
This register configures the cache line size field and the latency timer.
The following table shows the CFLT register bit fields.
Bit
Default
Description
31 – 16
0x00
Reserved
15 – 8
0x00
Configuration Latency Timer
Specifies, in units of PCI bus clocks, the value of the latency timer of the
KSZ8842-PMQL/PMBL. When the KSZ8842-PMQL/PMBL asserts FRAME_N,
it enables its latency timer to count. If the KSZ8842-PMQL/PMBL deasserts
FRAME_N prior to count expiration, the content of the latency timer is ignored.
Otherwise, after the count expires, the KSZ8842-PMQL/PMBL initiates
transaction termination as soon as its GNT_N is deasserted.
7 – 0
0x00
Cache Line Size
Specifies, in unit of 32-bit words (Dword), the system cache line size.
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