參數(shù)資料
型號(hào): KSZ8842-PMQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 52/119頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-PMQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-PMQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品:
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3348-ND - IC ETHERNET SW 2PORT 100-LFBGA
576-3089-ND - IC ETHERNT SW 2PORT PCI 100LFBGA
576-2121-ND - IC ETHERNET SW 2PORT PCI 128PQFP
576-1513-5-ND - IC SWITCH 10/100 32BIT 128-PQFP
其它名稱: 576-1636
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
38
M9999-100207-1.5
Bit
Description
28
IPCKG IP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct IP checksum for outgoing frames
that contains IP protocol header. The KSZ8842-PMQL/PMBL supports only a standard IP
header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit in the
transmit mode register should always be set.
This bit is used as a per-packet control when the IP checksum generate bit in the transmit
mode register is not set.
This bit should be always set for multiple-segment packets.
27
TCPCKG TCP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct TCP checksum for outgoing
frames that contains IP and TCP protocol header. The KSZ8842-PMQL/PMBL supports only
a standard IP header, i.e., IP with a 20 byte header. When this feature is used, ADD CRC bit
in the transmit mode register should always be set.
This bit is used as a per-packet control when the TCP checksum generate bit in the transmit
mode register is not set.
This bit should be always set for multiple-segment packets.
26
UDPCKG UDP Checksum Generate
When set, the KSZ8842-PMQL/PMBL will generate correct UDP checksum for outgoing
frames that contains a IP and UDP protocol header. The KSZ8842-PMQL/PMBL supports
only a standard IP header, i.e., IP with a 20 byte header. When this feature is used, ADD
CRC bit in the transmit mode register should always be set.
This bit is used as a per-packet control when the UDP checksum generate bit in the transmit
mode register is not set.
25
TER Transmit End of Ring
When set, indicates that the descriptor pointer has reached its final descriptor.
The KSZ8842-PMQL/PMBL returns to the base address of the list, forming a descriptor ring.
24
Reserved
23 – 20
SPN Switch Engine Destination Port Map
When set, this field indicates the destination port(s) where the packet will be forwarded to.
If bit 20 is set, it indicates the packet was received from port 1. If bit 21 is set, it indicates the
packet was received from port 2.
Setting all ports to 1 will cause the switch engine to broadcast the packet.
Setting all bits to 0 has no effect. The switch engine forwards the packet according to its
internal switch lookup algorithm.
This field is valid only when the last descriptor is set.
(Bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.)
19 – 11
Reserved
10 – 0
TBS Transmit Buffer Size
Indicates the size, in bytes, of the transmit data buffer.
If this field is 0, the KSZ8842-PMQL/PMBL ignores this buffer and moves to the next
descriptor.
The following table shows the TDES2 register bit fields.
Bit
Description
31 - 0
Buffer Address
Indicates the physical memory address of the buffer.
There is no limitation on the transmit buffer address alignment.
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