參數(shù)資料
型號: KSZ8842-PMBL
廠商: Micrel Inc
文件頁數(shù): 30/119頁
文件大?。?/td> 0K
描述: IC ETHERNT SW 2PORT PCI 100LFBGA
特色產(chǎn)品: Micrel Drives Ethernet Into the Global Automotive World
標(biāo)準(zhǔn)包裝: 260
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1636-ND - BOARD EVALUATION KSZ8842-PMQL
其它名稱: 576-3089
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
18
M9999-100207-1.5
Ball
Number
Ball
Name
Type
Ball Function
K2
IRDYN
I/O
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]
during write data phases, indicates it is ready to accept data during read data phases. As a
target, it’ll monitor this IRDYN signal that indicates the master has put the data on the bus.
H3
TRDYN
I/O
PCI Target Ready
As a bus target, this signal is asserted low to indicate valid data phases on PAD [31:0] during
read data phases, indicating it is ready to accept data during write data phases. As a master,
it will monitor this TRDYN signal that indicates the target is ready for data during read/write
operation.
J3
STOPN
I/O
PCI Stop
This signal is asserted low by the target device to stop the current transaction
K3
IDSEL
I/O
PCI Initialization Device Select.
This signal is used to select the KSZ8842-PMQL/PMBL during configuration read and write
transactions.
H4
DEVSELN
I/O
PCI Device Select
This signal is asserted low when it is selected as a target during a bus transaction. As a bus
master, the KSZ8842-PMBL samples this signal to insure that the destination address for the
data transfer is recognized by a PCI target.
J4
REQN
O
PCI Request
The KSZ8842-PMBL will assert this signal low to request PCI bus master operation.
K4
GNTN
I
PCI Grant
This signal is asserted low to indicate to the KSZ8842-PMBL that it has been granted the PCI
bus master operation.
H5
PERRN
I/O
PCI Parity Error
The KSZ8842-PMBL as a master or target will assert this signal low to indicate a parity error
on any incoming data. As a bus master, it will monitor this signal on all write operations.
J5
SERRN
O
PCI System Error
This system error signal is asserted low by the KSZ8842-PMBL.This signal is used to report
address parity errors.
K5
CBE3N
I
K6
CBE2N
I
J6
CBE1N
I
H6
CBE0N
I
Command and Byte Enable
These signals are multiplexed on the same PCI pins. During the address phase, these lines
define the bus command. During the data phase, these lines are used as Byte Enables. The
Byte enables are valid for the entire data phase and determine which byte lanes carry
meaningful data.
K7
PAD31
I/O
PCI Address / Data 31
Address and data are multiplexed on the all of the PAD balls. The PAD pins carry the
physical address during the first clock cycle of a transaction, and carry data during the
subsequent clock cycles.
J7
PAD30
I/O
PCI Address / Data 30
H7
PAD29
I/O
PCI Address / Data 29
K8
PAD28
I/O
PCI Address / Data 28
J8
PAD27
I/O
PCI Address / Data 27
H8
PAD26
I/O
PCI Address / Data 26
K9
PAD25
I/O
PCI Address / Data 25
J9
PAD24
I/O
PCI Address / Data 24
K10
PAD23
I/O
PCI Address / Data 23
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