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參數(shù)資料
| 型號(hào)： | KS7314 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Digital Zoom(數(shù)字圖像放大) |
| 中文描述： | 數(shù)碼變焦（數(shù)字圖像放大） |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大小： | 186K |
| 代理商： | KS7314 |
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KS7314
DIGITAL ZOOM
Vertical mosaic initial line of execution
Fig. 8 Vertical mosaic timing diagram (8
×
8 mosaic)
VBLK
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HD
CCD OUTPUT
KS7314 INPUT
MOSAIC OUTPUT
12. Digital video interface
KS7314 has a built-in DVC interface for application to digital video camcorders. In other words, the
luminance and chroma signal output of KS7314 can be used as an input to DVC encorder, without the
need of transmitting the output to KS7306, which is the signal processor. For this purpose, it is able to
adjust chroma signal timing in DVC mode against luminance signal and synchronization signal
±
8CK by
the system clock unit. KS7314 takes the input of the DVC mode recognition signal and the delay
adjustment value for the chroma signal from the micom.
13. Delay adjust
The processing delay developed in the process of electronic zooming should be compensated, and the
compensation can be achieved by delaying the signals related to active display of image, equal to the
electronic zoom processing delay. Namely, the input of signals CBLK, CSYNC, and CBF from the digital
camera processor(DCP) is taken to process and then entered back to DCP. The vertical delay is not
adjusted particulary in the electronic zoom process, now that PBLK is used in DCP as the line memory
reset. The signal gets readily processed before the image effective pixel process and thus vertical delay
is not considered. The electronic zoom processing delay lasts 20 system clock in total and it develops to
28 system clock for KS7314 in DVC mode.
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