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參數(shù)資料
| 型號： | KS7314 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Digital Zoom(數(shù)字圖像放大) |
| 中文描述： | 數(shù)碼變焦（數(shù)字圖像放大） |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 186K |
| 代理商： | KS7314 |
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KS7314
DIGITAL ZOOM
4. KS7314 input video data format
Fig. 3 Electronic zoom input video data format(4:1:1)
5. Line memory reset signal (LBLK) generation
x
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
x
Rm1
Rl1
Bm1
BI1
Rm2
RI2
Bm2
BI2
Rm3
UVCK
YI<7:0>
CI<3:0>
PCK
36CK
LBLKD
LBLK
HD
PBLK
Fig.
3
illustrates the video data format input to KS7314, fed from KS7306. The Luminance and
chroma D Data are in the 4:1:1 format, and the chroma data is entered in sequence of (R-Y) LSB,
(B-Y) MSB, and (B-Y) LSB. The UVCH signal distinguishs R-Y from B-Y. The LBLKO is the signal
used to reset the counter during the process of generating the READ/WRITE address of the line
memory. The duration in which LBKO is at high level is the effective pixel section. KS7314
generates LBLK signal that is used as the counter reset signal of line memory address self-
contained in the line memory address of KS7314. Considering that 28CK is developed while
processing the effective data of KS7306, LBLK is delayed to create LBLKD for use as a reset signal
of the line memory counter.
The chroma input of 4 formation is restructered to 8 bit signal before the application to the
interpolation.
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| KS74AHCT02N | 制造商:Samsung Semiconductor 功能描述: |
| KS74AHCT05N | 制造商:Samsung Electro-Mechanics 功能描述:Logic Circuit, HEX Inverter, AHCT/VHCT-CMOS, 14 Pin, Plastic, DIP |
| KS74AHCT138N | 制造商:Samsung Electro-Mechanics 功能描述:Demultiplexer/Decoder, 3 To 8 Line, 16 Pin, Plastic, DIP 制造商:Samsung Semiconductor 功能描述:Demultiplexer/Decoder, 3 To 8 Line, 16 Pin, Plastic, DIP |
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