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參數(shù)資料
| 型號： | KS7314 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Digital Zoom(數(shù)字圖像放大) |
| 中文描述： | 數(shù)碼變焦（數(shù)字圖像放大） |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 186K |
| 代理商： | KS7314 |
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KS7314
DIGITAL ZOOM
6. Vertical interpolation
Fig. 4-1 Vertical interpolation circuit
Fig. 4-2 H delay line timing specification for
vertical interpolation application
1H DELAY
LINE
to Horizontal
Interpolator
ALPHA
8
9
BETA
LHLD
ADDR
Horizontally
extended video data
x
x
1.22ns
1.1ns
0.1ns
0.1ns
0.1ns
0.1ns
5.69ns
0.1ns
ADDRESS
CK
WEN
OEN
DATA_IN
Fig.
4-1
is the vertical interpolating circuit applicable to both luminance and chroma signals. The vertical
video input data for the vertical interpolator is readily processed for horizontal video extension, using the
linememory at the former stage of luminance and the chroma signal horizontal extender. In the vertical
interpolation block, the interpolation coefficients Alpha and Beta, generated by the vertical interpolating
coefficient generator, are applied in the interpolation operation.
Fig.
4-2
dipicts 1H delay line timing specification applied to vertical interpolation. The function of READ
and WRITE is performed in the method of READ first and WRITE second, in 2 cycles of the linememory
clock. The AC timing above should be regarded as the minimum.
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