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參數(shù)資料
| 型號(hào)： | KM736V790 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Pipelined Burst SRAM(128Kx36位同步流水線脈沖靜態(tài) RAM) |
| 中文描述： | 128K × 36至位同步流水線突發(fā)靜態(tài)存儲(chǔ)器（128K × 36至位同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 317K |
| 代理商： | KM736V790 |
KM736V790
128Kx36 Synchronous SRAM
- 14 -
Rev 1.0
May.
1998
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
Data
Address
CLK
ADS
64-Bits
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
128Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
128Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:16]
A
[17]
A
[0:16]
A
[17]
A
[0:16]
I/O
[0:71]
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
ADDRESS
[0:n*]
Data Out
(Bank 0)
OE
Data Out
(Bank 1)
WRITE
CS
1
A
n+1*
ADV
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
t
SS
t
SH
A1
Q2-2
Q2-4
Q2-3
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
t
CD
t
LZC
Q2-1
A2
t
AS
t
AH
Don
′
t Care
Undefined
*NOTES
n = 14 32K depth,
15 64K depth, 16 128K depth, 17 256K depth
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